Reading PCIe data space cause an error

Hi Luhui,

Please provide more information about your test setup.

1. Which one is RC and EP on your setup?

2. Have you using TI provide example project? please share your project file.

Thanks,

Thanks for your replies！

    I  used  C6657 as RC and FPGA as EP, My DSP configuration as follows:

    The appendixis my project,   now  I read from address 0x60400000, the DSP core produce a MDMA bus error and a DSP memory protection fault.  I think it seems like the XMC has a incorrect configuration.

5226.TestPCIe.rar

This is the screenshot when reading from address 0x60400000

Hi Luhui,

I am also think it seems like the XMC has a incorrect configuration. Please share your XMC configuration code.

Take a look at below link and share your PCIe local/remote configuration register dump.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/282303.aspx

Thanks,

This is my DSP configuration:
XMC Configuration:
XMPAXL0 0x000000BF
XMPAXH0 0x0000001E
XMPAXL1 0x800000BF
XMPAXH1 0x8000001E
XMPAXL2 0x100000F6
XMPAXH2 0x2100000B
XMPAXL3 0x00C000FF
XMPAXH3 0x0C000013
XMPAXL4 0x00000080
XMPAXH4 0x00000000

RC PCIe Application register configuration:
CMD_STATUS 0x00000007
CFG_SETUP 0x00010000
OB_SIZE 0x00000003
ENDIAN 0x00000000
OB_OFFSET0_INDEX 0x10000001
OB_OFFSET0_HI 0x00000000
IB_BAR0 0x00000001
IB_START0_LO 0x70000000
IB_START0_HI 0x00000000
IB_OFFSET0 0x00000000

RC(C6657) Configuration:
STATUS_COMMAND 0x00180006
BAR[0] 0x10000000
BAR[1] 0x70000000
BUSNUM 0x00000000
DEV_STAT_CTRL 0x00002810
DEV_STAT_CTRL2 0x00000000

EP(Cyclone V) Configuration:
VENDOR_DEVICE_ID 0x10EE10EE
STATUS_COMMAND 0x00100006
BAR[0] 0x10000000
BAR[1] 0x10400000

I did some tests further, when I read frome 0x60000000, the value of PCIE_UNCERR changed to 0x4000 and the PCIE_CERR changed to 0x2000, So I think it seems like that a PCIe cpmpletion timeout error cuase the MDMA timeout error interrupt, and I'm not sure this cause a memory protection fault further;  But I set the DEV_STAT_CTRL2 to 0x00000000, that means the completion timeout value is 50 s to 50 ms, and I observed the interval between FPGA received request packet and sent completion packet is 80 ~ 100ns.

Now I really do not know what the problem is.  Thanks for your reply.

Hi Luhui,

I think your MPAX register configuration not blocked the 0x60000000 address.

I am not expert on MPAX, For my understanding your MPAX registers settings as follows:

• Register 0 value is 0000001E 000000BF -> correspondent to 2G mapping of internal memory into itself.

• Register 1 value is 8000001E 800000BF -> maps the 2G external memory 8000 0000 to ffff ffff into the 36 bit range 8 0000 0000 to 8 7fff ffff.

• Register 2 value is 2100000b 100000f6 -> Maps (again) 4K starting at address 0x21000000 to address 1 0000 0000. This is the DDR EMIF configuration registers. Note that if the same memory range is defined in multiple MPAX registers, the higher MPAX register translation is used.

• Registers 3 value is 0C00 0013 00C0 00FF -> Maps 1M memory starting at address 0x0C000000 to address 1 00C0 0000.

• Registers 4 to 15 values are 0000 0000 0000 0080 which basically points to empty memory regions.

Thanks,

Hi Ganapathi,

I'm very thanks for your reply.

I set the MPAL4 = 0x6000001E 060000BF, and the error still occur when read from 0x6000000. 

Thanks again for your help, I appreciate it!

Hi Luhui,

We also experience the same problem and get the same output pattern while reading from pcie. The occurence is not deterministic. Have you found any solution?

Regards,

Hasan