problem of GPMC comunicate with fpga

i change the board-am335xevm.c as upon. is that ok? 

this is the write function in my gpmc_drive.

i have debug this for a long time ,but i still have no idea .so come here for help.can anyone help me.

Hi,

What software version are you using?

What is the value of your GPMC_CONFIG7 register?

thanks for your repley ，

i have solved this problem but thers is a new one.

if i change the STNOR_GPMC_CONFIG1 0x00251000 to 0x00001000 (disable the wait pin function),the gpmc will be work.

but if i want to use wait1 for write access.how can i do it. 

Do you have anything connected to GPMC_WAIT1? Which processor pin are you using? Is the pinmux for this pin correct? What is your WAIT1 active level? Have you configured Bit 9 in the GPMC_CONFIG Register (section 7.1.6.9 in the AM335X TRM Rev. K)?

hi,Biser.

 1,i connect GPMC_WAIT1 to my FPGA .

 2,and i set GPMC_WAIT1 like this, {"gpmc_clk.gpmc_wait1", OMAP_MUX_MODE2 AM33XX_PIN_INPUT_PULLUP},

3.my GPMC_WAIT1 active low i set GPMC_CONFIG Register = 0x00000012(wait1 activ low),

4,GPMC_IRQENABLE Register  = 0x 00000201(enable wait1 interrupt)

5，STNOR_GPMC_CONFIG1 0x00211010 (WAIT input pin is WAIT1,WAIT pin is monitored for write accesses)

when i set all of this.

the gpmc can't write any word to FPGA .the wait1 keeps in 1. so what should i do?

joke ness said:

3.my GPMC_WAIT1 active low i set GPMC_CONFIG Register = 0x00000012(wait1 activ low)

Why do you set bit 4 in this register to 1? Try GPMC_CONFIG Register = 0x00000002

i have try it but it still don't work.should i request a irq for wait1?

Please check if you fulfill this requirement: WRACCESSTIME must be set so that the wait pin is at a valid state two GPMC clock cycles before WRACCESSTIME completes (see section 7.1.3.3.8.3.3 of the AM335X TRM Rev. K).

#define STNOR_GPMC_CONFIG1 0x00211010
#define STNOR_GPMC_CONFIG2 0x00080800
#define STNOR_GPMC_CONFIG3 0x00020201
#define STNOR_GPMC_CONFIG4 0x06020602
#define STNOR_GPMC_CONFIG5 0x00060707
#define STNOR_GPMC_CONFIG6 0x060000c2

do they have any problem the WRACCESSTIME is 6, WRONTIME is 2.

See section 7.1.5.1.5 in the AM335X TRM Rev. K. What seems strange to me is the write cycle time is shorter than the chip select time. Another thing is the GPMC_CONFIG1 bit 4=1 (TIMEPARAGRANULARITY x2 - this means that all timings are multiplied by 2 - TRM section 7.1.3.3.8.3.8).

Hi,Biser.

i have changed them 

#define STNOR_GPMC_CONFIG1 0x00211000
#define STNOR_GPMC_CONFIG2 0x00080800
#define STNOR_GPMC_CONFIG3 0x00020201
#define STNOR_GPMC_CONFIG4 0x06020602
#define STNOR_GPMC_CONFIG5 0x00060808
#define STNOR_GPMC_CONFIG6 0x060000c2

but i still can't write any word into my fpga.

if i want use wait pin should i request a irq for it in my driver? 

I do not see the wait pin changing state in your timing diagram.

i want write some data into fifo on  FPGA. if the fifo is full,i active the wait pin(wait = 0).if the wait is 1,i can write data into fifo.

in the time diagrame i don't write any word into fifo so the wait is 1.

Can you post the value of GPMC_CONFIG Register (offset = 50h)?

hi,Biser

do you know what is motorola mode ,i found some information on website ,it says that can't use wait in motorola mode,but  can use wait in intel mode,i don't know what is intel mode and motorola mode.

GPMC_CONFIG Register = 0x00000012

wow ,it works .thank you so much!

i‘m sorry to say that it still doesn't work .there is another problem. now i can write data into FIFO,but when the FIFO is full, the wait been set active(wait = 1). the GPMC still write data into FIFO.

Here you will have to scope inside the single write cycle and see when does the WAIT signal change state.

when the fifo is full the wait signal will change .

GPMC_PREFETCH_CONFIG1  bits[5~4]

0h = Selects Wait0EdgeDetection
1h = Selects Wait1EdgeDetection
2h = Reserved
3h = Reserved

should i change this register?

No, this register is used only for NAND accesses. Try playing with bits19-18 WAITMONITORINGTIME in GPMC_CONFIG1.

i'v tried it ,it still don't work,i don't why,when i changed GPMC_CONFIG Register into WAIT1 active high,i can write into gpmc,when WAIT1 active low i can't?

I'm sorry, I am not able to help more on this. I think the problem is how your FPGA implements WAIT. From the TRM:

7.1.3.3.8.3.3 Wait Monitoring During an Asynchronous Write Access
When wait-pin monitoring is enabled for write accesses (GPMC_CONFIG1_i[21] WAITWRITEMONITORING bit = 1), the WAIT-invalid timing window is defined by the WRACCESSTIME field. WRACCESSTIME must be set so that the wait pin is at a valid state two GPMC clock cycles before WRACCESSTIME completes.

ok,thanks !