• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 100 subscribers
  • Views 628 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6655 UPP in Transit mode

dave k
Intellectual 305 points

We are using the UPP bus on the C6655 to interface to an FPGA.  We have a loop back test which uses the B channel as the transmit from the DSP and the A channel a a receive from the FPGA.  We are seeing the B channel transmit more data then it is programmed for. 

When we operate at 16.67MHz (set  UPICR(27 to 24) = 9 ie. 1000M / 3 / 2 / (9 + 1))

we see 1 extra word transferred across the UPP channel B. 

When we operate at 57MHz (set set  UPICR(27 to 24) = 2 ie. 1000M / 3 / 2 / (2 + 1))

we see 4 extra words transferred across the UPP channel B.

This is true wether we do a line size of 64, 128 or 256.  We are transferring only 1 window and 1 buffer.  We are using the internal clock for the transmit side.  Here are the register settings.

UPP_UPPID = 0x44231100

UPP_UPPCR = 0x00000088

UPP_UPDLB = 0x00000000

UPP_UPCTL = 0x02020006

UPP_UPICR = 0x32383238

UPP_UPIVR = 0xaaaabbbb

UPP_UPTCR = 0x03030303

UPP_UPISR = 0x00000000

UPP_UPIER = 0x00000000

UPP_UPIES = 0x00001f1f

UPP_UPIEC = 0x00001f1f

UPP_UPEOI = 0x00000000

UPP_UPID0 = 0x81132880

UPP_UPID1 = 0x00010100

UPP_UPID2 = 0x00000100

UPP_UPIS0 = 0x81132980

UPP_UPIS1 = 0x00020000

UPP_UPIS2 = 0x00000020

UPP_UPQD0 = 0x81132980

UPP_UPQD1 = 0x00010100

UPP_UPQD2 = 0x00000100

UPP_UPQS0 = 0x81132a80

UPP_UPQS1 = 0x00020000

UPP_UPQS2 = 0x00000020

Any idea as to why we get the extra transfers?

  • 0
    TI__Mastermind 20790 points

    Dave,

    Transmit Mode: The FIFO is divided into blocks that can be set to 64, 128, or 256 bytes, configured by the TXSIZEA or TXSIZEB field in the uPP threshold configuration register (UPTCR).
    Please see the section "2.6.1 Step-by-Step Procedure" in the KeyStone Universal Parallel Port (uPP) User Guide.

    The below E2E post having the sample test code for UPP loopback, this may be useful to check the configuration your side except the loopback mode.
    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/202118/720332.aspx#720332

  • 0 in reply to Pubesh
    TI__Mastermind 20790 points

    Dave,

    Is that loopback test useful to compare your configuration? What is the status on your end?

  • 0 in reply to Pubesh
    Intellectual 305 points

    We setup a loopback test on the EVM6657.  The setup for the UPP lookback is  bytecount = 256, linecount = 2 . The UPP data increments by 1  every 16bit word-- Upp D0 toggles every UPP clock.  The attached trace shows the transfer of the data.  UPP D1 toggles 32 times for each UPP START pulse.  You can see the UPP EN does not go low right after the 32nd toggle of D1 in the 2nd line transferred, it actually stays high for a number of extra clocks.  We followed the procedure listed in 2.6.1 in the uPP User Guide.  The second attachment is a zoomed in look at the end of the transfer.

  • 0 in reply to dave k
    Intellectual 305 points

    Here is the full capture of the transfer, I could only attach 1 image on the last post.

  • 0 in reply to dave k
    TI__Mastermind 42545 points

    Hi Dave,

    The trailing clocks are unexpected. Have you captured the rising and falling edges of the enable signal with an oscilloscope? I want to see if these are distinct clock pulses or something caused by some ringing on the signal.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 305 points

    Bill

    Here is a scope trace of the UPP signals.  This is using the same program as the previous posts, so D0 is toggled every clock.  You can see from the trace that the Enable signal is high through out the transfer (the attached snapshot is of the end where you saw the multiple transitions on the logic analyzer trace from the previous post).  It appears the DSP is tristating the Enable and D0 lines at the end of the transfer, that is probably why the logic analyzer is seeing the toggles.  Can you verify that the bus is tristated when the transfer is completed?  I did not see this in the data sheet.

    upp signals.pdf
  • 0 in reply to dave k
    TI__Mastermind 42545 points

    Hi Dave,

    It looks like you've configured the channels to be in a high impedance state when idle. If you set UPICR.TRISB bit to 0 then the channel will not tristate after the enable is released. You will have to set a default value for the data bits using the UPIVR.VALB bits.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 305 points

    Bill

    That solves our problem, missed that in the data sheet.  Thanks for the help.