Hi,
From the c6748 TRM, we can find following information.
Channel 0 Control Register (C0CTRL) Field Descriptions
CLKEDGE : 0= Data is captured on rising edge of input clock.
1= Data is captured on falling edge of input clock.
Btw, from vpif.h in C6748_StarterWare_1_20_03_03, we can also find following code. It's the complete opposite.
/***************************************************************************/
/*
** Values that represent which edge of the pixel clock data changes phase on
** Used in the ClkedgeModeSelect APIs for all channels (3/2/1/0)
*/
/* Data changes on the rising edge of the pixel */
#define VPIF_CLKEDGE_RISING (1 << VPIF_C0CTRL_CLKEDGE_SHIFT)
/* Data changes on the falling edge of the pixel */
#define VPIF_CLKEDGE_FALLING (0 << VPIF_C0CTRL_CLKEDGE_SHIFT)
Which will be correct? I guess that TRM is wrong because TVP5157 on LCDKL138 is in falling mode and the CLKEDGE bit of vpif is 0.
Regards,
Devin