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vpif configuration

Hi,

From the c6748 TRM, we can find following information.

Channel 0 Control Register (C0CTRL) Field Descriptions

CLKEDGE :               0= Data is captured on rising edge of input clock.
                                     1= Data is captured on falling edge of input clock.

Btw, from vpif.h in C6748_StarterWare_1_20_03_03,  we can also find following code. It's the complete opposite.

/***************************************************************************/
/*
** Values that represent which edge of the pixel clock data changes phase on
** Used in the ClkedgeModeSelect APIs for all channels (3/2/1/0)
*/
 /* Data changes on the rising edge of the pixel */
#define VPIF_CLKEDGE_RISING                     (1 << VPIF_C0CTRL_CLKEDGE_SHIFT)
 /* Data changes on the falling edge of the pixel */
#define VPIF_CLKEDGE_FALLING                    (0 << VPIF_C0CTRL_CLKEDGE_SHIFT)

Which will be correct? I guess that TRM is wrong because TVP5157 on LCDKL138 is in falling mode and the CLKEDGE bit of vpif is 0.

 

Regards,

Devin

 

  • Hi,

    Thanks for your post.

    In my opinion, in the code, it actually VPIF driver API function "VPIFCaptureClkedgeModeSelect" to select the edge of the pixel clock that data is captured on. So, if you check the API code snippet below, the bit compliment of VPIF_C0CTRL_CLKEDGE which is ~VPIF_C0CTRL_CLKEDGE which is used in the code for C0 CTRL registers and thereby, if you take compliment the 31 bit which is CLKEDGE as per section 34.3.2 Channel 0 Control Register (C0CTRL) in the C6748 TRM, the bit would be become reverse.  Please check the code snippet in the below path:

    ~\Texas Instruments\pdk_C6748_2_0_0_0\C6748_StarterWare_1_20_03_03\drivers\vpif.c

    void VPIFCaptureClkedgeModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode)
    {
        unsigned int temp;
        if(channel==VPIF_CHANNEL_0)
        {
            temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_CLKEDGE;
            HWREG(baseAddr + C0CTRL) = temp | mode;
        }
        else if(channel==VPIF_CHANNEL_1)
        {
            temp = HWREG(baseAddr + C1CTRL) & ~VPIF_C1CTRL_CLKEDGE;
            HWREG(baseAddr + C1CTRL) = temp | mode;
        }
    }

    and as per the above code, the macro "VPIF_C1CTRL_CLKEDGE" is defined in the include file "hw_vpif.h"  and the file you can see in the below C6748 starterware installation path

    ~\Texas Instruments\pdk_C6748_2_0_0_0\C6748_StarterWare_1_20_03_03\include\hw\hw_vpif.h 

    and actually, the value of VPIF_C0CTRL_CLKEDGE is 0x80000000 and its compliment would be 0x7FFFFFFF which is used in the API "VPIFCaptureClkedgeModeSelect" to select the edge mode of the pixel clock. Kindly review the above code & validate the same.

    /* C0CTRL */

    #define VPIF_C0CTRL_CLKEDGE (0x80000000u)
    #define VPIF_C0CTRL_CLKEDGE_SHIFT (0x0000001Fu)

    Thanks & regards,

    Sivaraj K

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  • Hi Sivaraj,

    I already knew the VPIFCaptureClkedgeModeSelect function, where the important will be mode. Mode will select falling or rising. But I couldn’t find the function call from the entire SDK so couldn’t decide what “mode=1” means.

    void VPIFCaptureClkedgeModeSelect(unsigned int baseAddr, unsigned int channel, unsigned int mode)
    {
        unsigned int temp;
        if(channel==VPIF_CHANNEL_0)
        {
            temp = HWREG(baseAddr + C0CTRL) & ~VPIF_C0CTRL_CLKEDGE;
            HWREG(baseAddr + C0CTRL) = temp | mode;
        }

    ...

     

    }

    I'll do some more  tests with EVM.

    Regards, Devin

  • Hi Devin,

    Yes, you are right absolutely. While you debug the code, you will come to know exactly what exactly the pixel  clock edge mode it takes, it would be more appropriate, if you debug & test the code with the EVM board, you will have more clarity on this whether the clock is taking rising edge mode & falling edge mode. In my understanding, if you debug the code, it actually takes this API "VPIFCaptureClkedgeModeSelect" to select the pixel clock edge mode to be rising or falling mode.

    Kindly experiment the code and provide us more details.

    Thanks & regards,

    Sivaraj K

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