Question about intermediate transfer chaining function

Hi Oleg,

1. Is it a custom board?

2. How the FPGA is interfaced?

3. Where is the array 1024*8?

I am not clear on above post, please elaborate more to support you better.

Thank you.

Hi Rajasekaran,
Answer to first question - yes. I am reading data from FPGA and should devided it into eight cores.

Source array from FPGA

Destination array to DSP

Core 0 address 0x10850000

1024 bytes

Core 1 address 0x11850000

1024 bytes

Core 2 address 0x12850000

1024 bytes

Core 3 address 0x13850000

1024 bytes

Core 4 address 0x14850000

1024 bytes

Core 5 address 0x15850000

1024 bytes

Core 6 address 0x16850000

1024 bytes

Core 7 address 0x17850000

1024 bytes

I was writing short test for two cores, used PaRAM PARAM set and chained events.

Int32 _Edma_block_transfer_r02(float* block_src, float* block_dst, s32 _pa_cket) {

Int32 instNum = 1;
Uint8 channelNum = 1;
unsigned int ACNT = 2048;
unsigned int BCNT = 1;
unsigned int CCNT = 1;
unsigned int SRCBIDX = 0;// distance between source arrays
unsigned int DSTBIDX = 0x0;// distance between destination arrays


CSL_Status my_status;

Uint32 L2Offset;
L2Offset = 0x10000000 + 1 *_pa_cket; //8192
Uint32 src_core0_to_core1 = (Uint32)block_dst + 1024;

/* Module initialization */
CSL_edma3Init(&_context) ;

_hModule = CSL_edma3Open(&_edmaObj, instNum, NULL, &_status);
if (_status != CSL_SOK)
return -1;
/* Channel Open Global */
_chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL;
_chAttr.chaNum = channelNum;
_hChannel = CSL_edma3ChannelOpen(&_chObj, instNum, &_chAttr, &_status);
if (_hChannel == NULL)
return -2;

if (!instNum) {
CSL_edma3HwChannelSetupQue(_hChannel, CSL_EDMA3_QUE_1);
} else {
CSL_edma3HwChannelSetupQue(_hChannel, CSL_EDMA3_QUE_3);
}
CSL_edma3MapDMAChannelToParamBlock(_hModule, channelNum, 2);

/* Map the DMA Channel to the appropriate PARAM Block. */
my_status = CSL_edma3HwChannelSetupParam(_hChannel, 1) ;

/* Obtain a handle to parameter set */
_hParamBlock1 = CSL_edma3GetParamHandle(_hChannel, 1, &_status);
i

/* Setup the param set */
_myParamSetup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
6, \
CSL_EDMA3_TCC_NORMAL, \
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_EN, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR );
_myParamSetup.srcAddr = (Uint32)block_src;
_myParamSetup.dstAddr = (Uint32)block_dst + L2Offset;

_myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(ACNT,BCNT);
_myParamSetup.cCnt = CCNT;
_myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(SRCBIDX,DSTBIDX);
_myParamSetup.linkBcntrld= CSL_EDMA3_LINKBCNTRLD_MAKE(_hParamBlock2,2);
_myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
/* Setup the block1 entry */
CSL_edma3ParamSetup(_hParamBlock1,&_myParamSetup);
// new table
_myParamSetup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
6, \
CSL_EDMA3_TCC_NORMAL, \
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_EN, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR );
_myParamSetup.srcAddr = (Uint32)src_core0_to_core1;
_myParamSetup.dstAddr = (Uint32)block_dst + L2Offset + 0x01000000;

_myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(1024,1);
_myParamSetup.cCnt = CCNT;
_myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0);
_myParamSetup.linkBcntrld= CSL_EDMA3_LINKBCNTRLD_MAKE(_hParamBlock1,1);
_myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
/* Setup the block2 entry */
CSL_edma3ParamSetup(_hParamBlock2,&_myParamSetup);

/* Interrupt enable for the global region interrupts */
_regionIntr.region = CSL_EDMA3_REGION_GLOBAL;
_regionIntr.intr = (1<<6);
_regionIntr.intrh = 0;
my_status = CSL_edma3HwControl(_hModule,CSL_EDMA3_CMD_INTR_ENABLE,&_regionIntr);

if(my_status != CSL_SOK)
return -1;

my_status = CSL_edma3HwChannelControl(_hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
_regionIntr.region = CSL_EDMA3_REGION_GLOBAL;
_regionIntr.intr = 0;
_regionIntr.intrh = 0;

// my comment Poll on IPR bit 0
do {
my_status = CSL_edma3GetHwStatus(_hModule,CSL_EDMA3_QUERY_INTRPEND,&_regionIntr);
} while (!(_regionIntr.intr & 0x1));
/* Clear the pending bit */

my_status = CSL_edma3HwControl(_hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&_regionIntr);
if (my_status == CSL_ESYS_BADHANDLE) {
//printf("Error The handle passed is invalid into Channel Control\n");
return -2;
}
if (my_status == CSL_ESYS_INVPARAMS) {
//printf("Error The parameter passed is invalid into Channel Control\n");
return -3;
}
if (my_status != CSL_SOK) {
//printf("Error - Other Error into Channel Control\n");
return -1;
}

my_status = CSL_edma3HwControl(_hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&_regionIntr);
// my comment Poll on IPR bit 2
do {
CSL_edma3GetHwStatus(_hModule,CSL_EDMA3_QUERY_INTRPEND,&_regionIntr);
} while (!(_regionIntr.intr & 0x2));

return 0;
}

My test don't works.  I am running only the first part PaRAM - _hParamBlock1.

Where my errors?

Best regards,

     Oleg

Oleg,

Please have a look CSL based EDMA test code at: C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\example\edma

Take this as a reference, modify the code according to your requirement.

Oleg,

Great to hear. Thanks for the detailed steps to implemented on your side. This will be useful for future readers.