OMAP3530/MIcron MT46H32M32LFCM-6IT LPDDR compatibility question

Hi Rick,

We are using this part on our board with the OMAP3530 and it is working for us.  The SDRC settings found in u-boot are working.  As a side note we are trying to go to the 256MB version of that part, the MT46H64M32LFCM-6IT, and it is not working for us.

Dean

What kind of problems with the 256MB part?  I've modified x-loader/u-boot to support various memories and when ever I have problems, I can track it down to any one of: SDRC_CS_CFG or SDRC_MCFG_p (RASWIDTH/CASWIDTH).

Steve K.

Hello,

I plan on using the Micron DDR only MT46H64M32LFCM-5:A part as I don' t need the MCP NAND flash but just the DDR and figured that thread would be a good place to ask my question. Would someone from TI please confirm compatiblity of this part with OMAP3503? From my comparison of the POP MCP part MT29C4G48MAZAPAKQ-5 (recommended alternate to Beagle Board's PoP part) I see no issue with using this part.

Thank you very much.

Yves

Your suggestion of backing off the timings was a good one.  I found that in order for the part to work, I had to use 2 clocks in for the internal write to read command delay rather than just one as specified by the Micron data sheet.  Once I did this, the part has been working fine.

I'm curious how the experiment with the MT46H64M32LFCM-5:A being used as a LPDDR memory worked out for the OMAP3530.  We're working on a design for a client where the first pass was based on a Beagle Board, and we're now up against the problem that the combination NAND flash and LPDDR PoP chip used with it is about impossible to find.  So we're looking at alternative memories, one of which is the MT46H64M16LFCK-6:A to be attached as a pair to get us 32-bit bus width and 256MB overall memory space.  (Note that we're looking at the -6 part, which appears to be the LPDDR333 speed grade -- and is also the one that seems to be most available at this point.)

The board we're building is powered from a "wall wart" and will never be run from batteries, so squeezing every last electron out of the thing isn't a concern.  We also have plenty of PCB space (it's a 6"x6" board with quite a few Beagle Board components taken out and only one small additional I2C peripheral put back in), so the CUS ("Via Channel") package looks attractive as a way to keep bare PCB cost down.  But I'd sure like to hear from somebody who'd routed *two* non-PoP memories on a larger geometry PCB before committing to this in our own next PCB spin.

Hello,

I am hoping this thread is still alive.

I am trying to use the MT29C4G48MAZAPAKQ-5 IT PoP memory with the OMAP3530.

I have spent several days as well as used the Excel calculator sheet from the TI Wiki

trying to resolve SDRAM timing.

My issue is that when I have Autorefresh disabled in the OMAP Processor, I can read and write

to the SDRAM with about 90% success -- this is ok to me, as I know I am not refreshing, and I

expect bits to fade.

When I turn on the Autorefresh, I get garbled data everytime in all locations of the SDRAM. It is

never consistent, changes with each clock cycle, writes in garbage and reads garbage.

I have all the appropriate SDRC config registers for review if anyone would be willing to look at them, and will

post when requested.

Any ideas?

Hello, I cannot offer to review your registers. However we do have a working configuration with the MT29C4G48MAZAPAKQ-5 IT.

You are welcome to parse through our settings that I enclose below and provide feedback whether our not it was successful on your end. The following is the content of the ddr_config.c:

#define SDRC_POWER_DELAY                       (6 << 8)
#define SDRC_POWER_SRFRONRESET                 (1 << 7)
#define SDRC_POWER_SRFRONIDLEREQ               (1 << 6)
#define SDRC_POWER_EXTCLKDIS                   (1 << 3)
#define SDRC_POWER_PWDENA                      (1 << 2)
#define SDRC_POWER_CLKCTRL_1                   (1 << 4)
#define SDRC_POWER_CLKCTRL_2                   (2 << 4)
#define SDRC_POWER_AUTOCOUNT(x)                (x << 8)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_MCFG_0
//
//  Determines memory configuration registers.  Used to update SDRC_MCFG_0
//
//  Allowed values:
//

#define BSP_RASWIDTH_0                 (3 << 24)
#define BSP_CASWIDTH_0                 (5 << 20)
#define BSP_ADDRMUXLEGACY_0            (1 << 19)    // flexible address mux
#define BSP_RAMSIZE_0                  (128 << 8)    // 256mb SDRAM
#define BSP_BANKALLOCATION_0           (2 << 6)     // bank-row-column
#define BSP_B32NOT16_0                 (1 << 4)     // Ext. SDRAM is x32 bit.
#define BSP_DEEPPD_0                   (1 << 3)     // supports deep-power down
#define BSP_DDRTYPE_0                  (0 << 2)     // SDRAM is MobileDDR
#define BSP_RAMTYPE_0                  (1 << 0)     // SDRAM is DDR

#define BSP_SDRC_MCFG_0                (BSP_RASWIDTH_0 | \
                                        BSP_CASWIDTH_0 | \
                                        BSP_ADDRMUXLEGACY_0 | \
                                        BSP_RAMSIZE_0 | \
                                        BSP_BANKALLOCATION_0 | \
                                        BSP_B32NOT16_0 | \
                                        BSP_DEEPPD_0 | \
                                        BSP_DDRTYPE_0 | \
                                        BSP_RAMTYPE_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_MCFG_1
//
//  Determines memory configuration registers.  Used to update SDRC_MCFG_1
//
//  Allowed values:
//

#define BSP_RASWIDTH_1                 (3 << 24)
#define BSP_CASWIDTH_1                 (5 << 20)
#define BSP_ADDRMUXLEGACY_1            (1 << 19)    // flexible address mux
#define BSP_RAMSIZE_1                  (0 << 8)    // 0mb SDRAM
#define BSP_BANKALLOCATION_1           (2 << 6)     // bank-row-column
#define BSP_B32NOT16_1                 (1 << 4)     // Ext. SDRAM is x32 bit.
#define BSP_DEEPPD_1                   (1 << 3)     // supports deep-power down
#define BSP_DDRTYPE_1                  (0 << 2)     // SDRAM is MobileDDR
#define BSP_RAMTYPE_1                  (1 << 0)     // SDRAM is DDR

#define BSP_SDRC_MCFG_1                (BSP_RASWIDTH_1 | \
                                        BSP_CASWIDTH_1 | \
                                        BSP_ADDRMUXLEGACY_1 | \
                                        BSP_RAMSIZE_1 | \
                                        BSP_BANKALLOCATION_1 | \
                                        BSP_B32NOT16_1 | \
                                        BSP_DEEPPD_1 | \
                                        BSP_DDRTYPE_1 | \
                                        BSP_RAMTYPE_1)
//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_SHARING
//
//  Determines the SDRC module attached memory size and position on the SDRC
//  module I/Os..  Used to update SDRC_SHARING
//
//  Allowed values:
//
#define BSP_CS1MUXCFG                  (0 << 12)    // 32-bit SDRAM on [31:0]
#define BSP_CS0MUXCFG                  (0 << 9)     // 32-bit SDRAM on [31:0]
#define BSP_SDRCTRISTATE               (1 << 8)     // Normal mode

#define BSP_SDRC_SHARING               (BSP_CS1MUXCFG | \
                                        BSP_CS0MUXCFG | \
                                        BSP_SDRCTRISTATE)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_RFR_CTRL_0
//
//  SDRAM memory autorefresh control.  Used to update SDRC_RFR_CTRL_0
//
//  Allowed values:
//

//    * SDRC_RFR_CTRL_p - To set the refresh rate, get the Periodic Refresh interval tREFI from the memory datasheet. Note that this value is typcially in the us range. Some datasheets may refer //   to a "Refresh Interval time" in the millisecond range (64ms, for example), however, this value needs to be divided by the number of refresh cycles needed (typically 8000).
//         : ARCV
//
//        For 166MHz systems, tCK would be 6ns.
//        ARCV = tREFI/tCK - 50 = ARCV
//
//  tREFI = 7.8 us
//  tCK  = 6ns    ( 1/166Mhz)
//  
//        ARCV = (7.8us/6ns) - 50 = 1250 -> 0x4E2
//        Use same value for SDRC_RFR_CTRL_0.ARCV and SDRC_RFR_CTRL_1.ARCV

#define BSP_ARCV                       (0x4E2)
#define BSP_ARCV_0                     (BSP_ARCV << 8)  // Autorefresh counter val
#define BSP_ARE_0                      (1 << 0)         // Autorefresh on counter x1

#define BSP_SDRC_RFR_CTRL_0            (BSP_ARCV_0 | \
                                        BSP_ARE_0)
//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_RFR_CTRL_1
//
//  SDRAM memory autorefresh control.  Used to update SDRC_RFR_CTRL_1
//
//  Allowed values:
//
#define BSP_SDRC_RFR_CTRL_1             BSP_SDRC_RFR_CTRL_0

/*
DDR configuration
 * ACTIM_CTRLA -
 *  TWR = 15/6  = 3 (micron) MT29C4G48MAZAPAKQ-5 IT
 *  TDAL = Twr/Tck + Trp/tck = 15/6 + 15/6 = 3 + 3 = 6  (micron)
 *  TRRD = 10/6 = 2
 *  TRCD = 15/6 = 3
 *  TRP = 15/6  = 3
 *  TRAS = 40/6 = 7
 *  TRC = 55/6  = 10
 *  TRFC = 72/6 = 12 (micron)
 *
 * ACTIM_CTRLB -
 *  TCKE            = 1 (micron)
 *  XSR = 112.5/6   = 19  (micron)
*/

#define BSP_TRFC_0                     (12 << 27)   // Autorefresh to active
#define BSP_TRC_0                      (10 << 22)   // Row cycle time
#define BSP_TRAS_0                     (7 << 18)    // Row active time
#define BSP_TRP_0                      (3 << 15)    // Row precharge time
#define BSP_TRCD_0                     (3 << 12)    // Row to column delay time
#define BSP_TRRD_0                     (2 << 9)     // Active to active cmd per.
#define BSP_TWR_0                      (3 << 6)     // Data-in to precharge cmd
#define BSP_TDAL_0                     (6 << 0)     // Data-in to active command

#define BSP_SDRC_ACTIM_CTRLA_0         (BSP_TRFC_0 | \
                                        BSP_TRC_0 | \
                                        BSP_TRAS_0 | \
                                        BSP_TRP_0 | \
                                        BSP_TRCD_0 | \
                                        BSP_TRRD_0 | \
                                        BSP_TWR_0 | \
                                        BSP_TDAL_0)
          
//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_ACTIM_CTRLA_1
//
//  Determines ac timing control register A.  Used to update SDRC_ACTIM_CTRLA_1
//
//  Allowed values:
//
#define BSP_SDRC_ACTIM_CTRLA_1          BSP_SDRC_ACTIM_CTRLA_0

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_ACTIM_CTRLB_0
//
//  Determines ac timing control register B.  Used to update SDRC_ACTIM_CTRLB_0
//
//  Allowed values:
//

 #define BSP_TWTR_0                     (0x2 << 16)  // 1-cycle write to read delay
 #define BSP_TCKE_0                     (1 << 12)    // CKE minimum pulse width
 #define BSP_TXP_0                      (0x2 << 8)   // 5 minimum cycles
 #define BSP_TXSR_0                     (19 << 0)    // Self Refresh Exit to Active period

 #define BSP_SDRC_ACTIM_CTRLB_0         (BSP_TWTR_0 | \
           BSP_TCKE_0 | \
           BSP_TXP_0 | \
           BSP_TXSR_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_ACTIM_CTRLB_1
//
//  Determines ac timing control register A.  Used to update SDRC_ACTIM_CTRLB_1
//
//  Allowed values:
//
#define BSP_SDRC_ACTIM_CTRLB_1          BSP_SDRC_ACTIM_CTRLB_0

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_MR_0
//
//  Corresponds to the JEDEC SDRAM MR register.  Used to update SDRC_MR_0
//
//  Allowed values:
//
#define BSP_CASL_0                     (3 << 4)    // CAS latency = 3
#define BSP_SIL_0                      (0 << 3)    // Serial mode
#define BSP_BL_0                       (2 << 0)    // Burst Length = 4(DDR only)

#define BSP_SDRC_MR_0                  (BSP_CASL_0 | \
                                        BSP_SIL_0 | \
                                        BSP_BL_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_DLLA_CTRL
//
//  Used to fine-tune DDR timings.  Used to update SDRC_DLLA_CTRL
//
//  Allowed values:
//
#define BSP_FIXEDELAY                  (38 << 24)
#define BSP_MODEFIXEDDELAYINITLAT      (0 << 16)
#define BSP_DLLMODEONIDLEREQ           (0 << 5)
#define BSP_ENADLL                     (1 << 3)     // enable DLLs
#define BSP_LOCKDLL                    (0 << 2)     // run in unlock mode
#define BSP_DLLPHASE                   (1 << 1)     // 72 deg phase
#define BSP_SDRC_DLLA_CTRL             (BSP_FIXEDELAY | \
                                        BSP_MODEFIXEDDELAYINITLAT | \
                                        BSP_DLLMODEONIDLEREQ | \
                                        BSP_ENADLL | \
                                        BSP_LOCKDLL | \
                                        BSP_DLLPHASE)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_DLLB_CTRL
//
//  Used to fine-tune DDR timings.  Used to update SDRC_DLLB_CTRL
//
//  Allowed values:
//
#define BSP_SDRC_DLLB_CTRL             (BSP_SDRC_DLLA_CTRL)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_EMR2_0
//
//  Corresponds to the low-power EMR register, as defined in the mobile DDR
//  JEDEC standard.  Used to update SDRC_EMR2_0
//
//  Allowed values:
//
#define BSP_DS_0                       (0 << 5)    // Strong-strength driver
#define BSP_TCSR_0                     (0 << 3)    // 70 deg max temp
#define BSP_PASR_0                     (0 << 0)    // All banks

#define BSP_SDRC_EMR2_0                (BSP_DS_0 | \
                                        BSP_TCSR_0 | \
                                        BSP_PASR_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_EMR2_1
//
//  Corresponds to the low-power EMR register, as defined in the mobile DDR
//  JEDEC standard.  Used to update SDRC_EMR2_1
//
//  Allowed values:
//
#define BSP_SDRC_EMR2_1                (BSP_SDRC_EMR2_0)

setupddr()
{
       // Disable SDRC power saving mode
        CLRREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA);

        // update memory cofiguration
        OUTREG32(&pSdrc->SDRC_MCFG_0, BSP_SDRC_MCFG_0);
        OUTREG32(&pSdrc->SDRC_MCFG_1, BSP_SDRC_MCFG_1);
        OUTREG32(&pSdrc->SDRC_SHARING, BSP_SDRC_SHARING);

        // wait for at least 200us
        OALStall(2000);

        // set autorefresh
        OUTREG32(&pSdrc->SDRC_RFR_CTRL_0, BSP_SDRC_RFR_CTRL_0);
        OUTREG32(&pSdrc->SDRC_RFR_CTRL_1, BSP_SDRC_RFR_CTRL_1);

        // setup ac timings
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_0, BSP_SDRC_ACTIM_CTRLA_0);
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_1, BSP_SDRC_ACTIM_CTRLA_1);
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_0, BSP_SDRC_ACTIM_CTRLB_0);
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_1, BSP_SDRC_ACTIM_CTRLB_1);   

        // manual command sequence to start bank 0
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 0); // No Operation
        // wait for at least 200us
        OALStall(2000);
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 1); //Precharge all command - no parameter
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 2); //Autorefresh command - no parameter
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 2); //Enter deep-power-down - no parameter
        OUTREG32(&pSdrc->SDRC_MR_0, BSP_SDRC_MR_0);
  
  // re-enable power saving mode
        SETREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA | SDRC_POWER_SRFRONIDLEREQ);

        // update sdrc dll timings
        OUTREG32(&pSdrc->SDRC_DLLA_CTRL, BSP_SDRC_DLLA_CTRL);
        OUTREG32(&pSdrc->SDRC_DLLB_CTRL, BSP_SDRC_DLLB_CTRL);
       
        // update sdram characteristics
        OUTREG32(&pSdrc->SDRC_EMR2_0, BSP_SDRC_EMR2_0);
        OUTREG32(&pSdrc->SDRC_EMR2_1, BSP_SDRC_EMR2_1);
}

Regards,

Yves,

Thank you for the reply. Your configurations have definitely helped. However, I have a few questions.

1. Can you shed light on why you configured CS1 to be a zero size block of memory?

2. Your Twtr in BSP_SDRC_ACTIM_CTRLB is defined as a 2 cycle write to read delay, but the C comment

says 1 cycle.

3. It appears that your BSP_SDRC_DLLA_CTRL register runs in unlocked mode, and you implement the FIXED_DELAY

option in this same register. Specifically, how did you determine/analyze/configure that setting appropriately?

4. Also, why did you choose the 72 degree setting for the BSP_SDRC_DLLA_CTRL.DLLPHASE?

Thank you very much for your help, this discussion is very helpful.

yves vaillant said:

Hello, I cannot offer to review your registers. However we do have a working configuration with the MT29C4G48MAZAPAKQ-5 IT.

You are welcome to parse through our settings that I enclose below and provide feedback whether our not it was successful on your end. The following is the content of the ddr_config.c:

#define SDRC_POWER_DELAY                       (6 << 8)
#define SDRC_POWER_SRFRONRESET                 (1 << 7)
#define SDRC_POWER_SRFRONIDLEREQ               (1 << 6)
#define SDRC_POWER_EXTCLKDIS                   (1 << 3)
#define SDRC_POWER_PWDENA                      (1 << 2)
#define SDRC_POWER_CLKCTRL_1                   (1 << 4)
#define SDRC_POWER_CLKCTRL_2                   (2 << 4)
#define SDRC_POWER_AUTOCOUNT(x)                (x << 8)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_MCFG_0
//
//  Determines memory configuration registers.  Used to update SDRC_MCFG_0
//
//  Allowed values:
//

#define BSP_RASWIDTH_0                 (3 << 24)
#define BSP_CASWIDTH_0                 (5 << 20)
#define BSP_ADDRMUXLEGACY_0            (1 << 19)    // flexible address mux
#define BSP_RAMSIZE_0                  (128 << 8)    // 256mb SDRAM
#define BSP_BANKALLOCATION_0           (2 << 6)     // bank-row-column
#define BSP_B32NOT16_0                 (1 << 4)     // Ext. SDRAM is x32 bit.
#define BSP_DEEPPD_0                   (1 << 3)     // supports deep-power down
#define BSP_DDRTYPE_0                  (0 << 2)     // SDRAM is MobileDDR
#define BSP_RAMTYPE_0                  (1 << 0)     // SDRAM is DDR

#define BSP_SDRC_MCFG_0                (BSP_RASWIDTH_0 | \
                                        BSP_CASWIDTH_0 | \
                                        BSP_ADDRMUXLEGACY_0 | \
                                        BSP_RAMSIZE_0 | \
                                        BSP_BANKALLOCATION_0 | \
                                        BSP_B32NOT16_0 | \
                                        BSP_DEEPPD_0 | \
                                        BSP_DDRTYPE_0 | \
                                        BSP_RAMTYPE_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_MCFG_1
//
//  Determines memory configuration registers.  Used to update SDRC_MCFG_1
//
//  Allowed values:
//

#define BSP_RASWIDTH_1                 (3 << 24)
#define BSP_CASWIDTH_1                 (5 << 20)
#define BSP_ADDRMUXLEGACY_1            (1 << 19)    // flexible address mux
#define BSP_RAMSIZE_1                  (0 << 8)    // 0mb SDRAM
#define BSP_BANKALLOCATION_1           (2 << 6)     // bank-row-column
#define BSP_B32NOT16_1                 (1 << 4)     // Ext. SDRAM is x32 bit.
#define BSP_DEEPPD_1                   (1 << 3)     // supports deep-power down
#define BSP_DDRTYPE_1                  (0 << 2)     // SDRAM is MobileDDR
#define BSP_RAMTYPE_1                  (1 << 0)     // SDRAM is DDR

#define BSP_SDRC_MCFG_1                (BSP_RASWIDTH_1 | \
                                        BSP_CASWIDTH_1 | \
                                        BSP_ADDRMUXLEGACY_1 | \
                                        BSP_RAMSIZE_1 | \
                                        BSP_BANKALLOCATION_1 | \
                                        BSP_B32NOT16_1 | \
                                        BSP_DEEPPD_1 | \
                                        BSP_DDRTYPE_1 | \
                                        BSP_RAMTYPE_1)
//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_SHARING
//
//  Determines the SDRC module attached memory size and position on the SDRC
//  module I/Os..  Used to update SDRC_SHARING
//
//  Allowed values:
//
#define BSP_CS1MUXCFG                  (0 << 12)    // 32-bit SDRAM on [31:0]
#define BSP_CS0MUXCFG                  (0 << 9)     // 32-bit SDRAM on [31:0]
#define BSP_SDRCTRISTATE               (1 << 8)     // Normal mode

#define BSP_SDRC_SHARING               (BSP_CS1MUXCFG | \
                                        BSP_CS0MUXCFG | \
                                        BSP_SDRCTRISTATE)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_RFR_CTRL_0
//
//  SDRAM memory autorefresh control.  Used to update SDRC_RFR_CTRL_0
//
//  Allowed values:
//

//    * SDRC_RFR_CTRL_p - To set the refresh rate, get the Periodic Refresh interval tREFI from the memory datasheet. Note that this value is typcially in the us range. Some datasheets may refer //   to a "Refresh Interval time" in the millisecond range (64ms, for example), however, this value needs to be divided by the number of refresh cycles needed (typically 8000).
//         : ARCV
//
//        For 166MHz systems, tCK would be 6ns.
//        ARCV = tREFI/tCK - 50 = ARCV
//
//  tREFI = 7.8 us
//  tCK  = 6ns    ( 1/166Mhz)
//  
//        ARCV = (7.8us/6ns) - 50 = 1250 -> 0x4E2
//        Use same value for SDRC_RFR_CTRL_0.ARCV and SDRC_RFR_CTRL_1.ARCV

#define BSP_ARCV                       (0x4E2)
#define BSP_ARCV_0                     (BSP_ARCV << 8)  // Autorefresh counter val
#define BSP_ARE_0                      (1 << 0)         // Autorefresh on counter x1

#define BSP_SDRC_RFR_CTRL_0            (BSP_ARCV_0 | \
                                        BSP_ARE_0)
//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_RFR_CTRL_1
//
//  SDRAM memory autorefresh control.  Used to update SDRC_RFR_CTRL_1
//
//  Allowed values:
//
#define BSP_SDRC_RFR_CTRL_1             BSP_SDRC_RFR_CTRL_0

/*
DDR configuration
 * ACTIM_CTRLA -
 *  TWR = 15/6  = 3 (micron) MT29C4G48MAZAPAKQ-5 IT
 *  TDAL = Twr/Tck + Trp/tck = 15/6 + 15/6 = 3 + 3 = 6  (micron)
 *  TRRD = 10/6 = 2
 *  TRCD = 15/6 = 3
 *  TRP = 15/6  = 3
 *  TRAS = 40/6 = 7
 *  TRC = 55/6  = 10
 *  TRFC = 72/6 = 12 (micron)
 *
 * ACTIM_CTRLB -
 *  TCKE            = 1 (micron)
 *  XSR = 112.5/6   = 19  (micron)
*/

#define BSP_TRFC_0                     (12 << 27)   // Autorefresh to active
#define BSP_TRC_0                      (10 << 22)   // Row cycle time
#define BSP_TRAS_0                     (7 << 18)    // Row active time
#define BSP_TRP_0                      (3 << 15)    // Row precharge time
#define BSP_TRCD_0                     (3 << 12)    // Row to column delay time
#define BSP_TRRD_0                     (2 << 9)     // Active to active cmd per.
#define BSP_TWR_0                      (3 << 6)     // Data-in to precharge cmd
#define BSP_TDAL_0                     (6 << 0)     // Data-in to active command

#define BSP_SDRC_ACTIM_CTRLA_0         (BSP_TRFC_0 | \
                                        BSP_TRC_0 | \
                                        BSP_TRAS_0 | \
                                        BSP_TRP_0 | \
                                        BSP_TRCD_0 | \
                                        BSP_TRRD_0 | \
                                        BSP_TWR_0 | \
                                        BSP_TDAL_0)
          
//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_ACTIM_CTRLA_1
//
//  Determines ac timing control register A.  Used to update SDRC_ACTIM_CTRLA_1
//
//  Allowed values:
//
#define BSP_SDRC_ACTIM_CTRLA_1          BSP_SDRC_ACTIM_CTRLA_0

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_ACTIM_CTRLB_0
//
//  Determines ac timing control register B.  Used to update SDRC_ACTIM_CTRLB_0
//
//  Allowed values:
//

 #define BSP_TWTR_0                     (0x2 << 16)  // 1-cycle write to read delay
 #define BSP_TCKE_0                     (1 << 12)    // CKE minimum pulse width
 #define BSP_TXP_0                      (0x2 << 8)   // 5 minimum cycles
 #define BSP_TXSR_0                     (19 << 0)    // Self Refresh Exit to Active period

 #define BSP_SDRC_ACTIM_CTRLB_0         (BSP_TWTR_0 | \
           BSP_TCKE_0 | \
           BSP_TXP_0 | \
           BSP_TXSR_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_ACTIM_CTRLB_1
//
//  Determines ac timing control register A.  Used to update SDRC_ACTIM_CTRLB_1
//
//  Allowed values:
//
#define BSP_SDRC_ACTIM_CTRLB_1          BSP_SDRC_ACTIM_CTRLB_0

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_MR_0
//
//  Corresponds to the JEDEC SDRAM MR register.  Used to update SDRC_MR_0
//
//  Allowed values:
//
#define BSP_CASL_0                     (3 << 4)    // CAS latency = 3
#define BSP_SIL_0                      (0 << 3)    // Serial mode
#define BSP_BL_0                       (2 << 0)    // Burst Length = 4(DDR only)

#define BSP_SDRC_MR_0                  (BSP_CASL_0 | \
                                        BSP_SIL_0 | \
                                        BSP_BL_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_DLLA_CTRL
//
//  Used to fine-tune DDR timings.  Used to update SDRC_DLLA_CTRL
//
//  Allowed values:
//
#define BSP_FIXEDELAY                  (38 << 24)
#define BSP_MODEFIXEDDELAYINITLAT      (0 << 16)
#define BSP_DLLMODEONIDLEREQ           (0 << 5)
#define BSP_ENADLL                     (1 << 3)     // enable DLLs
#define BSP_LOCKDLL                    (0 << 2)     // run in unlock mode
#define BSP_DLLPHASE                   (1 << 1)     // 72 deg phase
#define BSP_SDRC_DLLA_CTRL             (BSP_FIXEDELAY | \
                                        BSP_MODEFIXEDDELAYINITLAT | \
                                        BSP_DLLMODEONIDLEREQ | \
                                        BSP_ENADLL | \
                                        BSP_LOCKDLL | \
                                        BSP_DLLPHASE)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_DLLB_CTRL
//
//  Used to fine-tune DDR timings.  Used to update SDRC_DLLB_CTRL
//
//  Allowed values:
//
#define BSP_SDRC_DLLB_CTRL             (BSP_SDRC_DLLA_CTRL)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_EMR2_0
//
//  Corresponds to the low-power EMR register, as defined in the mobile DDR
//  JEDEC standard.  Used to update SDRC_EMR2_0
//
//  Allowed values:
//
#define BSP_DS_0                       (0 << 5)    // Strong-strength driver
#define BSP_TCSR_0                     (0 << 3)    // 70 deg max temp
#define BSP_PASR_0                     (0 << 0)    // All banks

#define BSP_SDRC_EMR2_0                (BSP_DS_0 | \
                                        BSP_TCSR_0 | \
                                        BSP_PASR_0)

//------------------------------------------------------------------------------
//
//  Define: BSP_SDRC_EMR2_1
//
//  Corresponds to the low-power EMR register, as defined in the mobile DDR
//  JEDEC standard.  Used to update SDRC_EMR2_1
//
//  Allowed values:
//
#define BSP_SDRC_EMR2_1                (BSP_SDRC_EMR2_0)

setupddr()
{
       // Disable SDRC power saving mode
        CLRREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA);

        // update memory cofiguration
        OUTREG32(&pSdrc->SDRC_MCFG_0, BSP_SDRC_MCFG_0);
        OUTREG32(&pSdrc->SDRC_MCFG_1, BSP_SDRC_MCFG_1);
        OUTREG32(&pSdrc->SDRC_SHARING, BSP_SDRC_SHARING);

        // wait for at least 200us
        OALStall(2000);

        // set autorefresh
        OUTREG32(&pSdrc->SDRC_RFR_CTRL_0, BSP_SDRC_RFR_CTRL_0);
        OUTREG32(&pSdrc->SDRC_RFR_CTRL_1, BSP_SDRC_RFR_CTRL_1);

        // setup ac timings
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_0, BSP_SDRC_ACTIM_CTRLA_0);
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLA_1, BSP_SDRC_ACTIM_CTRLA_1);
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_0, BSP_SDRC_ACTIM_CTRLB_0);
        OUTREG32(&pSdrc->SDRC_ACTIM_CTRLB_1, BSP_SDRC_ACTIM_CTRLB_1);   

        // manual command sequence to start bank 0
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 0); // No Operation
        // wait for at least 200us
        OALStall(2000);
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 1); //Precharge all command - no parameter
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 2); //Autorefresh command - no parameter
        OUTREG32(&pSdrc->SDRC_MANUAL_0, 2); //Enter deep-power-down - no parameter
        OUTREG32(&pSdrc->SDRC_MR_0, BSP_SDRC_MR_0);
  
  // re-enable power saving mode
        SETREG32(&pSdrc->SDRC_POWER, SDRC_POWER_PWDENA | SDRC_POWER_SRFRONIDLEREQ);

        // update sdrc dll timings
        OUTREG32(&pSdrc->SDRC_DLLA_CTRL, BSP_SDRC_DLLA_CTRL);
        OUTREG32(&pSdrc->SDRC_DLLB_CTRL, BSP_SDRC_DLLB_CTRL);
       
        // update sdram characteristics
        OUTREG32(&pSdrc->SDRC_EMR2_0, BSP_SDRC_EMR2_0);
        OUTREG32(&pSdrc->SDRC_EMR2_1, BSP_SDRC_EMR2_1);
}

 

Regards,

Hello,

Please check the inline answers to your questions:

1. Can you shed light on why you configured CS1 to be a zero size block of memory?

           As per the PoP Memory (MT29C4G48MAZAPAKQ-5) datasheet, CS1 is reserved for future use. So we are configuring CS1 size as 0.

From Part Number decoding: we have 1 NAND and 1 LPDRAM.

Please refer the information from the datasheet (Page-14). Chip select:

CS0# is used for a single LPDDR product.

CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs

 2. Your Twtr in BSP_SDRC_ACTIM_CTRLB is defined as a 2 cycle write to read delay, but the C comment says 1 cycle.

We have configured for 2 cycles read delay for MT29C4G48MAZAPAKQ-5. But not updated in the comment as 2 cycles.

 3. It appears that your BSP_SDRC_DLLA_CTRL register runs in unlocked mode, and you implement the FIXED_DELAY option in this same register. Specifically, how did you determine/analyze/configure that setting appropriately?

Since this is processor specific register and No additional information has given in OMAP35xx TRM, we kept the values as in OMAP EVM BSP.

 4. Also, why did you choose the 72 degree setting for the BSP_SDRC_DLLA_CTRL.DLLPHASE?

Since this is processor specific register and No additional information has given in OMAP35xx TRM, we kept the values as in OMAP EVM BSP.

Hi Yves,

I noticed you successfully configured the MT29C4G48MAZAP SDRAM.

I am having a problem with the NAND Flash portion.  Using pretty standard code from TI's x-loader, the portion of code (see below) that waits for a 'ready' status after a reset command hangs forever.  

I have reviewed the GPMC settings and they seem appropriate - they were in fact configured for a slower part.

Have you had success with this and would be willing to share your configuration?

Thank you,

-David 

---code snippet----

if(command == NAND_CMD_RESET){

unsigned char ret_val;

NanD_Command(NAND_CMD_STATUS);

do{

ret_val = READ_NAND(NAND_ADDR);/* wait till ready */

} while((ret_val & 0x40) != 0x40);

}

Hi,

 I need Power calculator for MT29C4G48MAZAPAKQ-5 IT .. Thank u

Hi Vivek,

Micron offers a power calculator for their parts.  You can find it here:

http://www.micron.com/support/dram/power_calc.html

Hi Steve,

We have a omap3evm based board with MT29C4G96MAZAPCJG-5 IT, everything is OK except suspend/resume. Are you aware of any issues with this chip?

Thank you.

Hi Rick,

I think there is some errata fixes for ddr stall after suspend resume

Regards

Jethin

Hi Dean,

Do you know 256 MB MT46H64M32LFCM -6 IT is compatible with DM3730 ?

Thanks

Hi ozer,

This seems to be a supported one. please share the datasheet

Regards

Jethin

hi Jethin

Thank you

1856.MT46.pdf

Ozer,

This will be supported by Omap

Regards

Jethin

Also valid for  DM3730 ?

Regards

Yes,

Regards

Jethin