OMAPL138 VPIF buffer management

HI,

Thanks for your post.

To my opinion, VPIF's first interrupt is actually the second frame[n+1] and frame[n] is usually for data storage happening in previous buffer, so, obviously VPIF interrupt signal will be asserted on the second frame[n+1] but the data would be stored in the previous frame/buffer which would be used in the second frame[n+1] for the next buffer. So, the previous data would be exchanged to next buffer to respond after VPIF interrupt assertion through VPIF ISR and obviously, memory address register would be latched after VPIF ISR.

To make it more clear, once CPU kicks off the VPIF at frame[n-1] but no video capture happens in this period, the VPIF starts to capture incoming picture data only at the first VPIF frame interrupt at frame[n] and storage starts, the data being stored in SDRAM during this frame period. So, the actual 1st frame data in frame[n] would be asserted by VPIF only after the second frame interrupt at frame[n+1] period, the VPIF starts to assert displaying picture data just after the VPIF reads the 1st frame output data  stored in SDRAM. So, you are right that the data exchange from the previous frame data buffer to the next frame data buffer in first ISR  and start assert to  display the output picture data of 1st frame only from the 2nd frame onwards, thereby, address register would be latched after first ISR.

Thanks & regards,

Sivaraj K

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