AM335x errors and questions in the EVM device tree

Mike Worster

I'm making my own device tree now, using the SDK7 AM335x EVM device tree as a reference. I've found some points in that device tree that look like errors, and some points that I just have questions on:

1) There appears to be a "off by 1" type naming convention in the code base. Example:

mmc1_pins_default: pinmux_mmc1_pins {
			pinctrl-single,pins = <
				0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */

Here the code talks about a setup for mmc0 pins, but this node's label is mmc1. I assume TI did this for some reason where label "mmc1" actually is talking about the AM335x MMC0 block. Can I get confirmation on this?

2) There appears to be an issue with the comments in the device tree's lcd node:

		lcd_pins_default: lcd_pins_default {
			pinctrl-single,pins = <
				0x20 0x01	/* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
				0x24 0x01	/* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
				0x28 0x01	/* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */

Here the comments state gpmc_ad8's mode 1 should be for lcd_data16, gpmc_ad9's mode 1 should be . However both the pin mux tool and the data sheet both state the link should be:

            gpmc_ad8.lcd_data23
            gpmc_ad9.lcd_data22
            gpmc_ad10.lcd_data21

Or an inverse relationship. Could I please get a confirmation that the comments in the EVM device tree are incorrect?

3) Various pins mux descriptions were set up using hardcoded values, such as the lcd_pins node:

0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */

Is there any reason these were set up with hardcoded values instead of using OR'd flags (like most of the rest of the device tree does)?

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi Mike,

For correct pin mux modes please refer to the AM335X Datasheet Rev. G, Table 4-1.

0 Mike Worster over 10 years ago in reply to Biser Gatchev-XID

Expert 1575 points

Thanks Biser, I'll take that as an answer to my #2 question (the code is wrong) any idea of that will get corrected in a future SDK release?

Still have question 1 & 3 open.

0 Brad Griffis over 10 years ago

TI__Guru*** 125430 points

Mike Worster said:
1) There appears to be a "off by 1" type naming convention in the code base. Example:
mmc1_pins_default: pinmux_mmc1_pins {
			pinctrl-single,pins = <
				0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */
Here the code talks about a setup for mmc0 pins, but this node's label is mmc1. I assume TI did this for some reason where label "mmc1" actually is talking about the AM335x MMC0 block. Can I get confirmation on this?

The important thing is the register offset and the configuration. As you have surmised the comment is correct (mmc0) but the label is incorrect (mmc1). I'm not sure why they chose those particular labels. Sometimes the internal specs number things differently than our TRM, or it could be a carryover from OMAP3 where we labeled the MMC ports 1, 2, 3... It can (should!) be changed. Patches are welcome!

Mike Worster said:

3) Various pins mux descriptions were set up using hardcoded values, such as the lcd_pins node:

0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */

Is there any reason these were set up with hardcoded values instead of using OR'd flags (like most of the rest of the device tree does)?

There are many authors/contributors to the code and unfortunately they did not use uniform coding conventions. Patches welcome! :-)

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AM335x errors and questions in the EVM device tree