Hi,
I am working on mcspi whith FIFO and DMA enabled for a Beaglebone board. I am using spidev_test application(Documentation/spi/spidev_test.c) for data transfer and for reception using loopback(MISO to MOSI).
Problems:-
1: When using MCSPI_TX0 and MCSPI_RX0 registers transfer stops at wait_for_completion and no tx and rx call back is happening.
2: With reference to TRM for module control while using DMA with FIFO enabled one register FDDA is used. This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has its data managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX(i) and MCSPI_RX(i) registers.
From this reference when i have used MCSPI_DAFTX and MCSPI_DAFRX (Address for MCSPI_DAFTX = 0x80 and MCSPI_DAFRX = 0xa0) insted of MCSPI_TX0 and MCSPI_RX0 and set FDAA to one at module control setup.
In this case dma_tx_callback is coming but before tx_callback getting error message "DMA synchronization event drop occurred with device 35". After tx_callback DMA transfer and reception started (because using loopback) but EOW timed out(endof word count) for transmition and because of EOW rx_callback is not happing. Below reference code for interrupt
if (tx != NULL) {
wait_for_completion(&mcspi_dma->dma_tx_completion);
dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
if (mcspi->fifo_depth != 0) {
irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
if (mcspi_wait_for_reg_bit(irqstat_reg,
OMAP2_MCSPI_IRQ_EOW) < 0)
dev_err(&spi->dev, "EOW timed out\n");
mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
OMAP2_MCSPI_IRQ_EOW);
}
}
So i want to know how to enable interrupt.
