Powering the AM335x with the TPS650250 in the Power Save Mode

Hi Biser,

Thank you for your reply.

Our customer will check the PLL power supplies.

Has TI tried that the TPS650250 in the Power Save Mode works for the AM335x?
 
Best regards,
 
Daisuke

I don't have information whether this use case has been tried, but as you noted in Figure 2 on the TPS650250 User's Guide the TPS650250 is in the fixed frequency PWM mode (MODE=High), so I think that's the mode that's been tested and supported..

Hi Biser,

Thank you for your reply.

I want to know whether the case of Power Save Mode (MODE=Low) has been tried. Is there not any information?

Best regards,
 
Daisuke

Judging from Figures 13 and 14 on the TPS650250 datasheet, your customer probably has excessive voltage ripple on the DCDC outputs in power save mode. I definitely think that this mode is unsuitable for use with AM335X, as the TPS650250 datasheet states that it should be used for light loads.

Hi Biser,

Thank you for your reply.

The DCDC outputs do not supply to the PLL power terminals of the AM335X. The LDO output is used.

In Power Safe MODE, PFM is used at light loads, PWM for higher loads. The "POWER SAVE MODE OPERATION" on the TPS650250 datasheet describes that the two modes can switch by the load current.

Is the Power Save Mode certainly unsuitable for use with AM335X?

Best regards,

Daisuke

Yes, in my opinion it is unsuitable. Figure 2 on the TPS650250 User Guide explicitly shows that the MODE pin should be tied high.

Hi Biser,
 
Thank you for your reply. Sorry for my late reply.

Our customer wants to use the Power Safe MODE because a battery is used for the 5V source supply.

For TPS65910Ax, all DCDC output are set to the pulse skip mode in the EEPROM Configuration. For TPS650250, why can the PFM mode not be used?

VDD_CORE, VDD_MPU, and VDD_RTC are supplied from TPS650250 DCDC1.
In the Power Safe MODE, each DCDC output can be forcibly in the PWM mode by using a resistor to provide additional load (approximately 100mA) between the DCDC and Vss. If using the resistor for the DCDC1, the DDR PLL issue does not occur.
If using the resistor, the noise on the DCDC1 output is approximately 10mVp-p. If not, it is approximately 20mVp-p.

What are the limitations of peak-to-peak supply noise for VDD_CORE, VDD_MPU, and VDD_RTC?

Best regards,

Daisuke

Hi Biser,
 
Thank you for your reply. Sorry for my late reply.
 
The noise on the PLL supplies does not seem to exceed the limitations, but a ferrite bead is not used.
 
Our customer will check whether the TPS650250 DCDC1 output is not unstable when it switches to a PWM mode from a PFM mode.
 
Best regards,
 
Daisuke