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AM3354 design questions

Jaden Ghylin102047
Expert 1140 points
Other Parts Discussed in Thread: TPS65910A, AM3354

 

  1.  I’m using the RTC on the TPS65910A to power up the system from the off state.  Is there any reason I need to use the RTC on the AM3354 at all?  Right now, I don’t have an XTAL, and I’ve disabled the RTC LDO.
  2. With the TPS65910A work with 1.35V DDR3L?  I thought we could program the output voltage of SWIO to 1.35V, but when I was going through the datasheet,  it specifies 1.5V DDR3, and the EEPROM has it defaulting to 1.5V.
  3. GPMC_WPN and GPMC_wait0 are on VDDSHV3 (3.3V) according to the pin mux utility and is giving a power domain error when configuring the GMPC.  The rest of the GMPC lines I’m using are on VDDSHV1 (1.8V).  Can I still use GPMC_WPN as configured if I add a level shifter?
  4. Similarly, on the pin mux utility, I’m using Mode 1 for all of my RMII Pins except REFCLK, MDC, and MDIO are Mode 0.  Is this a problem?
  5. I just want to verify my understanding of the GPIO interrupt operation:  two interrupts can be generated per GPIO bank and the status register will tell you which of the 32 gpio pins triggered the interrupt?
  6. Is there any reason to power USB1_VBUS if that USB module isn’t being used?  Should it be left unconnected?

-Jaden

  • 0
    TI__Guru**** 393215 points

    Hi Jaden,

    Jaden Ghylin102047 said:
     I’m using the RTC on the TPS65910A to power up the system from the off state.  Is there any reason I need to use the RTC on the AM3354 at all?  Right now, I don’t have an XTAL, and I’ve disabled the RTC LDO

    This would depend on your use case. If you do not need the AM335X internal RTC it can be tied as shown in http://processors.wiki.ti.com/index.php/AM335x_Schematic_Checklist#RTC

    Jaden Ghylin102047 said:
    With the TPS65910A work with 1.35V DDR3L?  I thought we could program the output voltage of SWIO to 1.35V, but when I was going through the datasheet,  it specifies 1.5V DDR3, and the EEPROM has it defaulting to 1.5V.

    The TPS65910A doesn't have a 1.35V version. However DDR3L is backward compatible with DDR3 and can work at 1.5V.

    Jaden Ghylin102047 said:
    GPMC_WPN and GPMC_wait0 are on VDDSHV3 (3.3V) according to the pin mux utility and is giving a power domain error when configuring the GMPC.  The rest of the GMPC lines I’m using are on VDDSHV1 (1.8V).  Can I still use GPMC_WPN as configured if I add a level shifter?

    Yes, this is correct. For GPMC_WAIT0 all that should be needed is an external pullup to 3.3V because it's an input signal to the AM335X and is normally driven by open-drain output.

    Jaden Ghylin102047 said:
    Similarly, on the pin mux utility, I’m using Mode 1 for all of my RMII Pins except REFCLK, MDC, and MDIO are Mode 0.  Is this a problem?

    If the Pinmux tools doesn't show an I/O set violation there is no problem.

    Jaden Ghylin102047 said:
    I just want to verify my understanding of the GPIO interrupt operation:  two interrupts can be generated per GPIO bank and the status register will tell you which of the 32 gpio pins triggered the interrupt?

    Yes, this is correct.

    Jaden Ghylin102047 said:
    Is there any reason to power USB1_VBUS if that USB module isn’t being used?  Should it be left unconnected?

    See this wiki: http://processors.wiki.ti.com/index.php/AM335x_Schematic_Checklist#If_USB0_or_USB1_is_not_used...

  • 0 in reply to Biser Gatchev-XID
    TI__Guru 62855 points

    I would like to comment on the answer Biser provided for your question about needing a level shifter on the GPMC WPN and WAIT0 signals.  His answer is true if the attached memory device does have an issue with the respective open-drain outputs being pulled up to 3.3 volts.  A level shifter may still be needed if these outputs are not rated for 3.3 volts.

    Regards,
    Paul