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DDR3 ECC width

Kzk
Genius 5785 points


Hello,

Could you tell me the bit width needed for DDR3 ECC?  I heard that 4 bit ECC lacks for 32 bit data. So I searched for this information. I saw that the bit width needs log2(N)+2.

Ex)
64bit data (N=6); ECC=6+2=8 -> total=72bit
32bit data (N=5); ECC=5+2=7 -> total=39bit? (40bit)

DDR3 controller on C6657 has 36 bit only (data 32bit + ECC 4bit). Is that enough?

Regards,
Kazu

  • 0
    TI__Mastermind 43660 points

    Hello Kazu,

    Your understanding is absolutely correct.

    The C6657 device has a 32-bit IF with 4 additional check bits for ECC support creating a 36-bit interface. The controller calculates an 8-bit ECC value for every 64-bit quanta of data that also needs to be 64-bit aligned. For a 32-bit interface, the approach is to perform atleast two read backs to get min 64-bits of data or multiples of 64 bits. For each 64-bit read back, the controller will use the two 4 check bits to form an 8-bit ECC word to use for error correction/detection.

    Hope this helps for you.

    Regards,

    Senthil

     

  • 0 in reply to Senthilkumar Srinivasan
    Genius 5785 points

    Hello Senthil,

    Thank you for your quick reply. I understand. If I use K2E and DDR3 with 36-bit, its controller has Read-Modify-Write module. When K2E writes 8-bit data into DDR3, RMW reads and writes back 64-bit data. The controller will also use the two 4 bits to form an 8-bit ECC, right?

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Mastermind 42545 points

    Hi Senthil,

    If you are doing an 8-bit write to the DDR3, the K2E will use the RMW to read the 64bit word, modify the byte in question, recalculate the ECC for the entire 64bits and then write the value back to DDR memory. Note that all accesses to the DDR use an 8 word burst. A byte write will actually result in a a read burst of eight 64bit words, the modification of the byte and a burst write of eight 64bit words with ECC. You can see that byte accesses to DDR are not very efficient.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Genius 5785 points

    Hello Bill,

    Thank you for your information. I'm thinking about K2E with 36-bit data DDR3; Three 16-bit SDRAMs (including 4 bits of ECC). If I write 8-bit data, K2E will read eight 32-bit words, write eight 32-bit words and write eight 4-bit ECCs. The eight 4-bit ECCs means four pairs of 8-bit ECCs. Is my understanding correct?

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Genius 14322 points

    Hi,

     

    I did not see an answer to the above question about the behavior of the K2E 32-bit DDR interface with ECC. Could someone confirm, since the TRM only speaks about the 64-bit interface.

     

    Additionally do all memory controller assume that the same kind of DDR devices have to be used? What I am trying to say is that if 2x 16-bit DDR devices are being used to make up the 32-bit interface, there needs to be a third 16-bit DDR device for the ECC. Even though the ECC would only be 4-bit wide. There could not be an 8-bit DDR device for the ECC, is that correct?

     

    Thanks!

    --Gunter

     

  • 0 in reply to Gunter Schmer
    TI__Mastermind 42545 points

    Hi Gunter,

    The memory controller uses a single bit of ECC for each byte lane so a 64bit data bus would use 8 bits of ECC and a 32bit data bus would use 4 bits of ECC. 

    Usually the ECC memory device will be the same as the data memory devices but not always. Remember that the DDR3 memories are configured using the mode register set command (MRS). The mode registers are set using values on the address/command bus and are written to all the memories on the chain simultaneously. The memory used for ECC must have the same timing and the same mode register definition and the data memories.

    Regards,

    Bill