VC5505 Random bootloader ROM start up time?

Hi Ed,

How are you measuring the bootloader start time?

The order that the bootloader searches for a valid boot image is NOR Flash, NAND Flash, SPI EEPROM, I2C EEPROM, then MMC/SD.

I have measured the time between reset and the bootloader's first read from NOR Flash consistently as 7ms. Additionally, I have measured the transfer speed from NOR flash consistently as 188,090 Bytes/sec. Therefore, you should be able to boot as much as ~55,000 Bytes from NOR flash within 300ms. (0.007s + 55000 / 188090  = 0.299s)

I have tested this calculation and was able to boot from a 60,542 Byte boot image in NOR Flash in 322 ms.

Check out the C5505 Bootloader Appnote for additional details about the bootloader.

Hope this helps.

Regards,
Mark

Hi Mark,

We are running the EVM and USB stick independently from CCS so that they will enter the bootloader device search.  We are powering up the boards and measuring the time from reset to the first NAND flash chip select.  Both boards are populated with an early device: TMXVC5505D94AE67W, is it possible that the early devices have different characteristics?

We have run some more tests and it would appear that the 7mS delay occurs for a manual reset with the board powered.  If the board is powered up from cold and the delay from reset is measured then the delay is random and long.  If you power down and then power up the boards within 3 seconds the delay is still 7mS, however if this power down cycle is greater than 3 seconds the delay increases, at greater than 5 seconds power cycle the delay is 300mS+,  this would imply some sort of capacitive linked stabilitiy issue.  Any ideas?  We will be running our design from cold to save power and because of the application it will have to respond from cold very quickly.

Thanks, Ed

Hi Ed,

It sounds like your EVM has the RTC_VDD supercap populated on C54. Newer EVM's do not have this capacitor populated. This capacitor supplies RTC_VDD during sleep

mode, but must be charged before RTC_VDD reaches steady state.

Try to lift the + terminal of this capacitor from the board. I think this will resolve your random boot times.

See Page 7 of the C5505 EVM Schematic.

Regards,
Mark

Hi Mark,

The supercap isn't populated so it must be something else.

Regards,

Ed

Sorry Ed,

I still haven't been able to reproduce the 300-400ms delay between RESET and the start of boot from NAND Flash... I have been measuring the delay between RESET and ALE (Address latch enable) with the memory daughter card removed from the EVM, and the largest delay observed has been 88ms.

Have you taken any more measurements? I would be interested in your boot times from the NOR Flash.

I could keep digging into this problem, or we could swap EVMs - you send us your EVM and we'll send you the latest EVM with PG1.4 Silicon.

Let me know,
Mark

Hi Mark,

Thanks again for the reply.  We are monitoring the reset line and the chip select (EM_CS2) and measuring the time between reset going high and chip select pulsing low (no boot code), we will try and test some NOR code booting using the memory card to see if there is any difference, is there an app for loading boot code to NOR flash?.  Unfortunately we are not able to swap EVM boards for testing as we are in the process of developing application code for the EMIF interface and cannot really afford the down time.  The chips that we will be using in our prototypes in  a month or so are TMX320VC5505DZCH, are they a later revision that may not suffer the same delays?  Also, there seems to be some conflict between the datasheet and the EVM/USB Stick schematics regarding what to do with the RSV1 & RSV2 pins, should we tie them to the core voltage or not?

Kind regards,

Ed