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66AK2H12/06 USB3.0 FLADJ_30MHz field

RY9983
Guru 10570 points
Other Parts Discussed in Thread: 66AK2H12

Hello,
I am using 66AK2H12/06 USB3.0 interface.
There is no detail FLADJ_30MHz field in FLADJ register.
And, its register is defferent from xHCS standard by Intel.

66AK2H : FLADJ (Jitter adjustment and other pseudo-static parameters)
xHCI standard : FLADJ (Frame Length Adjustment Register)

You can see detail of the xHCI standard
http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf
(P280) 5.2.4 Frame Length Adjustment Register (FLADJ)

Question:
Could you let me know about detail of FLADJ_30MHz ?
Can I have any documentation or article of it(FLADJ_30MHz)?

Best regards, RY

 

spruhj7 (P97) 3.1.24 FLADJ [Offset = 0x0704]

  • 0
    TI__Intellectual 1805 points

    RY,

    This register field is for HS Jitter Adjustment, and is connected to the FLADJ register defined in the xHCI spec in the PCI configuration space. It indicates the correction required to accommodate mac3 clock and utmi clock jitter to measure 125 μs duration.

    With fladj_30mhz =0, the high speed 125us micro-frame is counted for 123933ns. The value needs to be programmed in terms of high speed bit times in a 30 MHz cycle. Default value that needs to be driven is 32 (assuming 30 MHz perfect clock). Each count is equal to 16 high speed bit times. By default when this register is set to 32, it gives 125us interval. Now, based on the clock accuracy you can decrement the count or increment the count to get the 125 us uSOF window.

    Regards!
    Wen

  • 0 in reply to Wenzhong Liu
    Guru 10570 points

    Wen-san,

    Thank you so much for your response!
    Does your comment means that the fladj_30mhz corresponds to "Frame Length Timing Value" field in FLADJ in xHCI spec?

    I attach the FLADJ spec in xHCI.
    It seems fladj_30mhz value(your comment) is different from FLADJ Value in xHCI spec.

    I think it's 66AK2H device spec.
    Is my understanding correct?

    Best regards, RY

  • 0 in reply to RY9983
    TI__Intellectual 1805 points

    RY-san,

    I believe they are the same, eventhough I don't understand why the peripheral document uses the name - fladj_30mhz. But I believe, the programming value should be the same. Please notice that:

        1. In the USB Standard Spec, one bit increament of this FLADJ register corresponding
            to a 16 bits of HS data stream, running in around 480Mhz.

        2. The description of the FLADJ_30MHZ counter says -  the value needs to be programmed
             in terms of high speed bit times in a 30 MHz cycle. Since 480/30 = 16, one bit change of
             this counter still equal to 16 HS bit times RUNNING in 480MHz.

    Regards!
    Wen