• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 97 subscribers
  • Views 352 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Issue with IIC communication while talking to RTC

GKT
Prodigy 70 points
Other Parts Discussed in Thread: OMAP3530

Hi,

I am trying to talk to RTC chip using IIC communication. 
OMAP3530 is the master and RTC chip is slave. 
I am getting into an issue when during a write operation after 8 bit the slave pulls the SDA line low to acknowledge the transfer and at this point if the clock is interrupted by pulling the power to the processor, the RTC which is always powered by a backup battery holds the SDA line low indefinetly. So the next time when the master tries to talk it sees the bus as busy. 
Does any one suggest any software solution on how to tackle this issue.

Anything on the OMAP side that could supply some more clocks to allow the device to not hold the bus low?

Thanks,

Girish 

 

  • 0
    TI__Mastermind 43875 points

    Girish,

    Have you tried doing a dummy read of the device at powerup to see if it clears the indeterminate state of the RTC?

    You could possibly either temporarily configure the SCL port as a GPIO or tie a GPIO pin to the SCL signal and perform some dummy clocks at power up? If you try this don't forget that the GPIO will need to bahave like an open drain. The way to do this is to set the GPIO output state to be '0', then use the output enable (or direction) to toggle the clock. Output enabled for a logic 0 and output disabled for a logic 1.

    What is the part number for the RTC? Is there a datasheet available?

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 70 points

    Steve,

    Part Number of RTC is "M41T66".

    Also I2C 1 that is connected to RTC cannot be configured as a GPIO. 

    For the second option tieing a GPIO to SCL, I don't have a free GPIO at this point to use for this purpose.

    That is the reason why I am looking if I can implement any software solution that can avoid or possibly recover from this undetermined state.

     

    I haven't tried a dummy read at power up yet, but it looks like it is sensing the bus as busy. So I guess my attempt to dummy read won't get bus access.

    Am I right?

    Any more ideas appreciated.

    Thanks,

    Girish

     

  • 0 in reply to GKT
    TI__Mastermind 43875 points

    Girish,

    The issue is really that the I2C specification for multi-master does not account for the power being removed from part of the system.

    The only suggestions I have is to either try to find a GPIO or to move to I2C2, which would allow you to toggle the SCL line.

    I have not found a way to configure I2C1 to not be multi-master compliant.

    I could not see a way to clear the RTC either unfortunately.

    BR,

    Steve

  • 0 in reply to GKT
    TI__Mastermind 43875 points

    Girish,

    I have been told of a setting which may help resolve your problem.

    The I2C controller has a register called I2C_SYSTEST which may allow you to toggle the clock at start up in order to flush out any pending operations which may be locked. See section "18.4.9 System Test Mode" in the TRM

    I have not tries this, so can't comment further, but you should give this a try.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 70 points

    Steve,

    Just a couple of hours back one of our design engineers got this suggestion from another TI engineer.

    I am going to try this and see if this solves the issue.

    Thanks though!!

    Girish