boot from nand in C665x

1.  In the example provided on that thread the device boot the DSP from NAND and executes Idle command from internal memory. In order to confirm the device has booted and create a target configuration file in CCS and remove the GEL file that initializes the device (since in NAND boot RBL initializes the device) and connect to the DSP. You should see the DSP has exitted the L2ROM Memory and is executing in internal RAM memory (check program counter). You can load symbols from the .out file by selecting Run->Load Symbols and select you out file. In the Disassembly view you should see an idle instructton at the  DSP Program counter value.

2. ELF and COFF format should matter when you are creating the boot image as hex6x will simply reorganize the binary generated by the cl6x utility (compiler) it doesn`t modify the content of the code and data sections depending on type of binary.

3. Syntax for RMD files is provided as part of the hex6x documentation in tthe C6000 compiler documentation. Please refer to section 11 in the TMS320C6000 Assembly Language Tools v7.x User's Guide under ccsv5/tools/compiler/c600_7.x.x/doc and let us know if you have any further questions.

4. If you want to put code into DDR, you need to populate the DDR configuration table. I am providing a SPI boot example that initializes DDR you can do the same with NAND boot.

2084.SPIboot_ddr.zip

Critical steps are to populate the  BOOT_EMIF4_TBL_T  emif4Cfg strcuture in the code )and define it in the .emif4Cfg section (refer spiboot.c) that is placed at the top of the all the section placement in the linker command file (refer spiboot.cmd)

Regards,

Rahul

Dear Rahul,

Thanks for your help.

after two things are done, we can boot from nand to L2SRAM or DDR3 successfully, now.

1st: do the second reset.

Booting from a NAND flash device will fail when the C6657/C6655 at full speed. The root cause of the problem is that insufficient time is allowed for the NAND device to complete the initial reset command sent to it by the DSP ROM code. After sending the reset command, the DSP executes a wait loop(for time out). This wait loop allows a maximum number of iterations before halting and declaring that the NAND is not responding correctly. The wait loop does not allow enough time for the NAND to complete its initial reset sequence.

Proposed work arounds:

• Use the FPGA firmware on the system to first apply reset to the NAND flash device and then apply reset to C6657 device after the NAND device is ready.
• After a POR of the devicie, apply CPU reset. The CPU reset only restarts the RBL and allows the NAND flash device to complete its initial transition out of reset. This will work because NAND devices complete the second and subsequent reset sequences faster when compared to the initial reset sequence (5 micro-seconds vs. 300 micro-seconds) NAND boot can be made to work by simply taking C6657/C6655 back into reset and then releasing it from reset. This extra reset sequence must be done without cycling power to the NAND device. Resetting C6655/C6657 after an initial NAND boot attempt works since the wait loop is long enough for success on a second boot attempt)

2ed: change the switch configuration of SW5 to 100MHz

bcz we use 100MHz in our custom board, the default settings of SW5 is  50MHz.