am335x spi slave error

Hi,

What software are you using?

Looking at the AM335X TRM Rev. K section 24.3.1.9 MCSPI_CH0STAT=0x28 means that both FIFOs are empty and there is data in the MCSPI_TX0 register. See also sections 24.2.4.3 and 24.2.4.4. They state that:

"Transmitter register or FIFO (if enabled) content is always loaded into the shift register whether it has been updated or not. The event TX_underflow is activated accordingly, and does not prevent transmission."

I use u-boot from ti web. Am335x spi slave will receive image from another cpu as spi master for upgrading new software.

Yes, there is data (zero)in the MCSPI_TX0 register. But I never write any data to MCSPI_TX0. 

How can I clear this bad data and not affect the configuration of spi  module(make sure spi master do nothing)? It is the key problem I cared  about.

Once I initialized the spi slave, one zero always can be readed by another master. Is it a bug of am335x?

Thanks a lot.

This isn't a bug, it's expected behavior as explained above. If you disable the TX FIFO you shouldn't see this.

How can I clear this bad data and not affect the configuration of spi  module(make sure spi master do nothing)? SPI

Master never expect one zero when slave user  writes nothing. I have to clear the content that not belongs to me before meaningful transfer.

Thanks a lot.

If you disable the TX FIFO you shouldn't have this extra byte. Otherwise transmitter register should be loaded before McSPI is selected by an external SPI master device.

1. You mean that once MCSPI_TX0 registe has data, no way clear it? So you suggest to avoid the case?

2. " transmitter register should be loaded before McSPI is selected by an external SPI master device", could you tell me the detail operations about registers?

3. another quetion: spi as slave, how to set pin mux for spi pin for mode 0?

clk: receiver enable PULLDOWN

d0: receiver disable PULLDOWN output for slave MISO

d1: receiver enable PULLDOWN input data for slave MOSI

cs: receiver enable PULLUP

Thanks a lot.

1 + 2. I don't know your use case, so I cannot say which approach would be better. You could use FIFO and make the SPI master ignore the first byte that it receives. If you know exactly what the first byte value is you could preload it in the Slave transmitter.

3. This seems OK.

Thanks a lot;

Your answer is great!

The last question: Could you tell me the max bps for spi slave?  I found that at 8M bps, there is something wrong occasionally, but at 4M bps, the transmission is always OK. I can make sure the master has no problem.

There is no data for SPI Slave operation speed. The AM335X SPI Linux driver supports only Master mode.

I know what you said, but I care the speed(bps) that am335x as spi slave can support.

According to the AM335X Datasheet, Rev. G, Table 7-81, the maximum clock frequency for SPI Slave mode is 16MHz.