Reference Clock Termination in AMI Model

James Drohan

Other Parts Discussed in Thread: TMS320C6678

On the 6678 reference clock inputs like DDRCLKP / DDRCLKN, is the 100 ohm termination internal, and if so, is it captured in the AMI model? Our simulation does not appear to act like the termination is there, so would like to confirm.

Thanks,

Jim

over 11 years ago

0 Senthilkumar Srinivasan over 11 years ago

TI__Mastermind 43660 points

Hello James,

All differential clock inputs are implemented with Texas Instruments low jitter clock buffers (LJCBs). These input buffers include a 100 ohm parallel termination (P to N) and common mode biasing.

But i'm not sure the AMI model does include this termination. However i will check and update you on this.

Regards,

Senthil

0 James Drohan over 11 years ago in reply to Senthilkumar Srinivasan

Prodigy 40 points

I should correct that we are using IBIS model tms320c6678_4_2_1_r1p5b.ibs . Let us know if this supports simulation with the termination.

0 Senthilkumar Srinivasan over 11 years ago in reply to James Drohan

TI__Mastermind 43660 points

Hello James,

Unfortunately the 100 ohm parallel termination for DDRCLKP/N is not modeled in IBIS model.

Regards,

Senthil

0 Bill Taboada over 11 years ago in reply to James Drohan

TI__Mastermind 42545 points

Hi Jim,

A bug in the model for the LJCB clock input buffer was recently found. The LJCB does have internal 100 ohm termination but the IBIS model does not correctly assign the termination to the input pins. We are working to update the model. As a work-around, you can connect an external 100ohm resistor to the input pins in your simulation to emulate the internal termination. To be clear, this 100 ohm resistor in not needed on your board; it is only needed in the simulation to compensate for the bug.

Regards, Bill

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Reference Clock Termination in AMI Model