Hi
I noticed that the init_PLL() gel file routine that came with the evm CD, uses a PLLM value of 20, and has notes that say the input freq is 50 MHz. Yet the schematic (p5) and Fig 2-2 or the tech ref says that the SYSCLK input is 61.44 MHz.
With a PLLM of 20, would that be beyond the max freq of the chip? (1228.8 MHz)
Which is correct. The Tech Ref doc for th EVM board also states 61.44 MHz on Fig 2.2
Does the evmc6474 board have the 1000 or 1200 MHz part?
Thanks
-----------------------------------------GEL FILE evmv6474.gel--------------------------------------------
init_PLL()
{
int i;
int PLLM_val = 20; // 50 x 20 = 1000 MHz
int PREDIV_val = 1;
int PLLDIV4_val = 8;
int PLLDIV5_val = 4;
if (PLLM_val > 0 && PLLM_val < 32)
{
if ( (PREDIV_val > 0) && (PREDIV_val < 33) )
{
/* In PLLCTL, write PLLENSRC = 0 (enable PLLEN bit).*/
*(int *)PLLCTL_1 &= ~(0x00000020);
/* In PLLCTL, write PLLEN = 0 (bypass mode).*/
*(int *)PLLCTL_1 &= ~(0x00000001);
/* Wait 4 cycles of the slowest of PLLOUT or reference clock source (CLKIN).*/
for (i=0 ; i<100 ; i++);
/*In PLLCTL, write PLLRST = 1 (PLL is reset).*/
*(int *)PLLCTL_1 |= 0x00000008;
/*If necessary, program PREDIV and PLLM.*/
*(int *)PLLM_1 = PLLM_val - 1;
*(int *)PREDIV_1 = (PREDIV_val - 1) | 0x8000; /* set PLLDIV0 */
