c6678 pcie link training failed

woodyiy

Hi evetyone, I have an issue about PCIe communication between a c6678 custom board and a PowerPC board.They are connected with PCIe port, c6678 acts as EP and PowerPC acts as RC. I am running the PCIe example code in c6678 PDK(version:1.0.0.21),I only changed the PCIE_SERDES_CFGPLL.MPY bit field from 0x64 to 0x40, because my PCIESS reference clock input is 156.25MHz, but the LTSSM always stays among 0x1(DETECT_ACT),0x2(POLL_ACTIVE),0x6(DETECT_WAIT).My DIP switch settings are as followes: sw3:off,on,on,on sw4:on,on,on,on sw5:on,on,on,on sw6:on,on,on,on Can anyone give some suggestions? Thanks a lot! yours, tain eric

over 11 years ago

0 Raja over 11 years ago

TI__Guru* 81335 points

Hi Tain,

Please ensure that the power sequencing happens correctly. Please go through below wiki for more information.

http://processors.wiki.ti.com/index.php/PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

Thank you.

0 Ganapathi Dhandapani95 over 11 years ago in reply to Raja

TI__Mastermind 28085 points

Hi Tain,

In the MCSDK PCIe sample example, two DSP EVMs are used to test the PCIe driver. DSP 1 is configured as a Root Complex and DSP 2 is configured as End Point.

Once the PCIe link is established, the following sequence of actions will happen:

1. DSP 1 sends data to DSP 2 - DSP 2 waits to receive all the data

2. DSP 2 sends the data back to DSP 1

3. DSP 1 waits to receive all the data

4. DSP 1 verifies if the received data matches the sent data and declares test pass or fail.

MCSDK PCIe example is not directly support for your requirement. Please refer section "2.11.2 PCIe as End Point" on PCIe user guide and modified the example code for your requirement. PCIe End Point initialization setps are clearly explained in PCIe user guide document.

Thanks,

0 woodyiy over 11 years ago in reply to Raja

Intellectual 310 points

To Rajasekaran K, Thank you for your early reply, I checked your suggestion, but I still have one question.The power sequence says:“PCIe slot on PC host provides power and reference clock to PCIe module on EVM”, but in my design, common clock is not used, I configured the LINK_STAT_CTRL.COMMON_CLK_CFG=0 as described in PCIe user guide section 2.2, and the PCIESS still doesnot link.

0 Raja over 11 years ago in reply to woodyiy

TI__Guru* 81335 points

Hi Tain,

Please follow Ganapathi's suggestion on this subject,

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/369860/1300535.aspx#1300535

Thank you.

0 woodyiy over 11 years ago in reply to Raja

Intellectual 310 points

I am so sorry for the delay, because I donot know why i cannot open the login web page the other day. This problem has been solved. My colleague told me that the frequency of ref clk is 156.25MHz, and I believed that he is right, but actually the input ref clk is 125MHz.After the value of PCIE_SERDES_CFG.MPY is changed,link training works well now. Thanks a lot for your help. sincerely, eric

0 Ganapathi Dhandapani95 over 11 years ago in reply to woodyiy

TI__Mastermind 28085 points

Thanks for your update.

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c6678 pcie link training failed