Keystone II DDR3 byte lane swapping

Richard Yearsley

Other Parts Discussed in Thread: AM5K2E04

Hi,

I'm linking a Keystone II (AM5K2E04) to 4x 16-bit Micron DDR3 devices (MT41K128M16JT-125:K).

The DDR3 design guide mentions that data bits can be swapped within byte lanes, but not whether the byte lanes themselves can be swapped. I would like to swap the odd lanes with the even lanes e.g. 0-1, 2-3, 4-5, 6-7.

I've read in a few places that lanes can be swapped when using JEDEC compliant controllers, but just thought I'd check.

Can anyone see any issue with this?

Best regards,

Richard

over 11 years ago

0 Senthilkumar Srinivasan over 11 years ago

TI__Mastermind 43660 points

Hello Richard,

I think swapping is definitely ok byte wise as long as all the DQ lines in that byte and corresponding DQS/DQSn and DQM control signals are all grouped together and all the length matching requirements for these signals are met.

For example, DQ[7:0],DQS0/DQSN0,DQM0 can be connected to DQS[15:8],DQS1/DQSN1,DQM1 of a memory device and vice versa.

Regards,

Senthil

0 Richard Yearsley over 11 years ago in reply to Senthilkumar Srinivasan

Prodigy 210 points

Perfect, thank you Senthil.

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Keystone II DDR3 byte lane swapping