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Problems when moving taskStackSection to MSMCSRAM

Feng
Expert 2985 points

Hi TI expert,

My configuration:

C6670, CCS V5.3, Complier TI v7.4.1, SYS/BIOS v6.33.6.50.

I have the same code running on 4 cores of C6670. Every core runs three task, one is SRIO task(the highest priority) and the other two(the lower priority) are data processing task. The stacksize of the first data processing task  is 0x40000 bytes. And the stacksize of the other is 0x20000 bytes.

Then the L2 of each core is not enough to contain all the code. 

So I move some sections to MSMCSRAM like the codes in cfg file below

Program.sectMap[".idleTaskStackSection"] = "MSMCSRAM";
Program.sectMap[".taskStackSection"] = "MSMCSRAM";
Program.sectMap["const"] = "MSMCSRAM";

And I get the map file like this

MEMORY CONFIGURATION

         name            origin    length      used     unused   attr    fill
----------------------  --------  ---------  --------  --------  ----  --------
  L2SRAM                00800000   00100000  000dfc08  000203f8  RW X
  MSMCSRAM              0c000000   00200000  001343a0  000cbc60  RW X
  DDR3                  80000000   20000000  00000000  20000000  RWIX


SEGMENT ALLOCATION MAP

run origin  load origin   length   init length attrs members
----------  ----------- ---------- ----------- ----- -------
00800000    00800000    00059700   00059700    r-x
  00800000    00800000    000596e0   000596e0    r-x .text
  008596e0    008596e0    00000020   00000020    r-- .const.1
00859700    00859700    000389c8   00000000    rw-
  00859700    00859700    000389c8   00000000    rw- .far.1
008920d0    008920d0    000004b0   00000000    rw-
  008920d0    008920d0    000004b0   00000000    rw- .far.2
00892580    00892580    0001c59e   0001c59e    r--
  00892580    00892580    0001c59e   0001c59e    r-- .const.2
008aeb20    008aeb20    0000821a   0000821a    rw-
  008aeb20    008aeb20    0000821a   0000821a    rw- .fardata
008b6d40    008b6d40    00010080   00000000    rw-
  008b6d40    008b6d40    00008080   00000000    rw- tcp3DriverSection
  008bedc0    008bedc0    00008000   00000000    rw- tcp3DDataSection
008c6dc0    008c6dc0    00012080   00008000    rw-
  008c6dc0    008c6dc0    00008000   00008000    rw- .args
  008cedc0    008cedc0    00008000   00000000    rw- .stack
  008d6dc0    008d6dc0    00002080   00000000    rw- tcp3QueueDescrSection
008d8e40    008d8e40    0000019c   0000019c    r--
  008d8e40    008d8e40    0000019c   0000019c    r-- .switch.1
008d9000    008d9000    000004b0   000004b0    r-x
  008d9000    008d9000    00000200   00000200    r-x .vecs
  008d9200    008d9200    000002b0   000002b0    r-- .switch.2
008d94b0    008d94b0    000000b4   00000000    rw-
  008d94b0    008d94b0    000000b4   00000000    rw- .bss
008d9564    008d9564    000000d1   000000d1    rw-
  008d9564    008d9564    000000d1   000000d1    rw- .neardata
008d9638    008d9638    00000068   00000068    r--
  008d9638    008d9638    00000068   00000068    r-- .rodata
008d96a0    008d96a0    000001a0   00000000    rw-
  008d96a0    008d96a0    00000120   00000000    rw- .cio
  008d97c0    008d97c0    00000080   00000000    rw- tcp3DataSection
008d9840    008d9840    000063fc   000063fc    r--
  008d9840    008d9840    000063fc   000063fc    r-- .cinit
0c010000    0c010000    001219a0   00000000    rw-
  0c010000    0c010000    0007b8a0   00000000    rw- .Tran_Receive_buffer
  0c08b8a0    0c08b8a0    00060800   00000000    rw- .far:taskStackSection
  0c0ec0a0    0c0ec0a0    0003c000   00000000    rw- systemHeap
  0c1280a0    0c1280a0    00009900   00000000    rw- IRAM
0c131a00    0c131a00    00002880   00000000    rw-
  0c131a00    0c131a00    00002400   00000000    rw- .qmss
  0c133e00    0c133e00    00000480   00000000    rw- .cppi
0c134280    0c134280    00000180   00000180    rw-
  0c134280    0c134280    00000180   00000180    rw- .srioSharedMem

When I debug this code, I meet some problems.

Firstly, I load the codes in core0 and core0 runs the codes well.

Then I load the codes in core1 but core1 fails showing like below

The DSP core runs @ 983MHzDebug(Core 1): Waiting for SRIO to be initialized.
Debug(Core 1): SRIO can now be used.
SRIO start!
Core Num = 1
*********************************************
*******ICT Debug Info: SRIO Task Start*******
*********************************************
A0=0xc0cb858 A1=0x0
A2=0x1 A3=0xc131980
A4=0xc0ec4d8 A5=0xc0ec4c8
A6=0x8027 A7=0x1
A8=0x828d20 A9=0xc133d38
A10=0x847b2e A11=0xc0cb888
A12=0x847b78 A13=0x0
A14=0x1c9a1 A15=0x5400027
A16=0xc0ecb18 A17=0x0
A18=0xc0ec934 A19=0x1e0
A20=0x20 A21=0x0
A22=0x0 A23=0x0
A24=0x0 A25=0x1
A26=0x0 A27=0x0
A28=0x1088e0c0 A29=0x134
A30=0x34022e50 A31=0x8ae928
B0=0xc0ecbd0 B1=0x0
B2=0x0 B3=0x2000027
B4=0x0 B5=0x15000102
B6=0xc0ec4c8 B7=0x1
B8=0x8b5978 B9=0x8ae964
B10=0xc0cb88c B11=0x0
B12=0x0 B13=0x3
B14=0x8d94b0 B15=0xc0cb888
B16=0x0 B17=0x0
B18=0x2e40000 B19=0x0
B20=0x0 B21=0x2e4
B22=0x2e40000 B23=0x0
B24=0x0 B25=0x3000
B26=0x3000 B27=0x0
B28=0x0 B29=0x0
B30=0x2e4 B31=0xc0ecc54
NTSR=0x1000e
ITSR=0xf
IRP=0x85651a
SSR=0x0
AMR=0x0
RILC=0x0
ILC=0x0
Exception at 0x0
EFR=0x2 NRP=0x0
Internal exception: IERR=0x1
Instruction fetch exception
ti.sysbios.family.c64p.Exception: line 248: E_exceptionMin: pc = 0x00000000, sp = 0x0c0cb888.
To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePrint = true;'
xdc.runtime.Error.raise: terminating execution

After I debug step by step on core1, I find that the SRIO task with the highest priority can works well. Then SRIO task pend a semaphore and the data processing task with lower priority runs and the error information is printed in console.

Could anyone help me!?

Regards,

Feng

  • 0
    Expert 2985 points

    My cfg file is 2045.my.cfg

    My map file is 0247.my.txt

    The linker cmd file is 

    Fullscreen 5141.linker.txt Download 
    /*
 * Do not modify this file; it is automatically generated from the template
 * linkcmd.xdt in the ti.targets.elf package and will be overwritten.
 */

/*
 * put '"'s around paths because, without this, the linker
 * considers '-' as minus operator, not a file name character.
 */


-l"D:\Project\DSP\NJ\ICT_BBU_Proj_NJ\Debug\configPkg\package\cfg\ICT_BBU_Proj_pe66.oe66"
-l"C:\ti\ipc_1_24_03_32\packages\ti\sdo\ipc\lib\instrumented_e66\ipc\ipc.lib"
-l"C:\ti\pdk_C6670_1_1_2_6\packages\ti\drv\srio\lib\ti.drv.srio.ae66"
-l"C:\ti\pdk_C6670_1_1_2_6\packages\ti\drv\pa\lib\ti.drv.pa.ae66"
-l"C:\ti\pdk_C6670_1_1_2_6\packages\ti\drv\cppi\lib\ti.drv.cppi.ae66"
-l"C:\ti\pdk_C6670_1_1_2_6\packages\ti\drv\qmss\lib\ti.drv.qmss.ae66"
-l"C:\ti\pdk_C6670_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66"
-l"C:\ti\bios_6_33_06_50\packages\ti\sysbios\lib\instrumented_e66\sysbios\sysbios.lib"
-l"C:\ti\xdctools_3_23_04_60\packages\ti\targets\rts6000\lib\ti.targets.rts6000.ae66"
-l"C:\ti\xdctools_3_23_04_60\packages\ti\targets\rts6000\lib\boot.ae66"

--retain="*(xdc.meta)"


--args 0x8000
-heap  0x0
-stack 0x8000

MEMORY
{
    L2SRAM (RWX) : org = 0x800000, len = 0x100000
    MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000
    DDR3 : org = 0x80000000, len = 0x20000000
}

/*
 * Linker command file contributions from all loaded packages:
 */

/* Content from xdc.services.global (null): */

/* Content from xdc (null): */

/* Content from xdc.corevers (null): */

/* Content from xdc.shelf (null): */

/* Content from xdc.services.spec (null): */

/* Content from xdc.services.intern.xsr (null): */

/* Content from xdc.services.intern.gen (null): */

/* Content from xdc.services.intern.cmd (null): */

/* Content from xdc.bld (null): */

/* Content from ti.targets (null): */

/* Content from ti.targets.elf (null): */

/* Content from xdc.rov (null): */

/* Content from xdc.runtime (null): */

/* Content from ti.targets.rts6000 (null): */

/* Content from ti.sysbios.interfaces (null): */

/* Content from ti.sysbios.family (null): */

/* Content from ti.sysbios (null): */

/* Content from ti.sysbios.hal (null): */

/* Content from ti.sysbios.knl (null): */

/* Content from xdc.services.getset (null): */

/* Content from ti.csl (null): */

/* Content from ti.drv.qmss (null): */

/* Content from ti.drv.cppi (null): */

/* Content from ti.drv.pa (null): */

/* Content from ti.drv.srio (null): */

/* Content from ti.sysbios.gates (null): */

/* Content from ti.sysbios.heaps (null): */

/* Content from xdc.runtime.knl (null): */

/* Content from ti.sdo.ipc.interfaces (null): */

/* Content from ti.sysbios.syncs (null): */

/* Content from ti.sdo.ipc.family (null): */

/* Content from ti.sdo.utils (null): */

/* Content from ti.sysbios.family.c66 (null): */

/* Content from ti.sysbios.family.c64p (null): */

/* Content from ti.sysbios.family.c66.tci66xx (null): */

/* Content from ti.sysbios.xdcruntime (null): */

/* Content from ti.sysbios.family.c62 (null): */

/* Content from ti.sysbios.timers.timer64 (null): */

/* Content from ti.sysbios.family.c64p.tci6488 (null): */

/* Content from ti.sysbios.utils (null): */

/* Content from ti.catalog.c6000 (null): */

/* Content from ti.catalog (null): */

/* Content from ti.catalog.peripherals.hdvicp2 (null): */

/* Content from xdc.platform (null): */

/* Content from xdc.cfg (null): */

/* Content from ti.platforms.evm6670 (null): */

/* Content from ti.sdo.ipc.heaps (null): */

/* Content from ti.sdo.ipc (ti/sdo/ipc/linkcmd.xdt): */

SECTIONS
{
    ti.sdo.ipc.SharedRegion_0:  { . += 0x10000;} run > 0xc000000, type = NOLOAD
}


/* Content from ti.sdo.ipc.family.c647x (null): */

/* Content from ti.sdo.ipc.notifyDrivers (null): */

/* Content from ti.sdo.ipc.transports (null): */

/* Content from ti.sdo.ipc.nsremote (null): */

/* Content from ti.sdo.ipc.gates (null): */

/* Content from configPkg (null): */


/*
 * symbolic aliases for static instance objects
 */
xdc_runtime_Startup__EXECFXN__C = 1;
xdc_runtime_Startup__RESETFXN__C = 1;
TSK_idle = ti_sysbios_knl_Task_Object__table__V + 136;

SECTIONS
{
    .text: load >> L2SRAM
    .ti.decompress: load > L2SRAM
    .stack: load > L2SRAM
    GROUP: load > L2SRAM
    {
        .bss:
        .neardata:
        .rodata:
    }
    .cinit: load > L2SRAM
    .pinit: load >> L2SRAM
    .init_array: load > L2SRAM
    .const: load >> L2SRAM
    .data: load >> L2SRAM
    .fardata: load >> L2SRAM
    .switch: load >> L2SRAM
    .sysmem: load > L2SRAM
    .far: load >> L2SRAM
    .args: load > L2SRAM align = 0x4, fill = 0 {_argsize = 0x8000; }
    .cio: load >> L2SRAM
    .ti.handler_table: load > L2SRAM
    systemHeap: load >> MSMCSRAM
    tcp3DataSection: load >> L2SRAM
    tcp3DriverSection: load >> L2SRAM
    tcp3QueueDescrSection: load >> L2SRAM
    tcp3DDataSection: load >> L2SRAM
    .idleTaskStackSection: load >> MSMCSRAM
    const: load >> MSMCSRAM
    .vecs: load >> L2SRAM
    .far:taskStackSection: load >> MSMCSRAM
    xdc.meta: load >> L2SRAM, type = COPY

}

  • 0 in reply to Feng
    TI__Guru* 81335 points

    Hi,

    With smaller stack size, is the program run as expected in L2 memory?

    Please refer below threads and if it does not help you, please post the same query on TI-RTOS forum for faster response.

    http://e2e.ti.com/support/embedded/tirtos/f/355/t/297707.aspx

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/360619.aspx

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/231954.aspx

    http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/149427.aspx

    Thank you.

  • 0 in reply to Raja
    Expert 2985 points

    Hi Rajasekaran,

     

    Now, I take some setps like reducing the size of systemHeap, reducing the Program.heap from 81920 to 0x1, reducing the Program.argSize from 32768 to 0x4, moving the .taskStackSection and systemHeap from MSMCSRAM to L2RAM and moving the .text from L2RAM to MSMCRAM. Then the code runs well.

     

    But there are some confusions with me.

    1. When the .text in L2RAM, every core have its private .text to run. Now I have moved the .text from L2RAM to MSMCSRAM, the .text resides in one section of MSMCSRAM. All the 4 cores use the same .text. Are there some problems in  this situation?

    2. I have met another question. If I move any section of data to DDR3, there program will fail. But I have use the evmc6670l to initialize the DDR3. Are there some other configuration when I want to move some data or code to DDR3?

     

    Regards,

    Feng