DM365 PLL initialization in the boot process

Kevin Claycomb

During the boot process what pieces of code interact to change the PLL registers?

Is it all done up front in UBL or does U-Boot and Linux manipulate the PLL registers as well?

If they do can someone point me to the correct files to modify in order to change the default U-Boot and Linux PLL settings.

Thanks,

Kevin

over 15 years ago

0 Kevin Claycomb over 15 years ago

Intellectual 420 points

Some more information about the issue that brought this up. I have moved my custom design to the 270 MHz production silicon. The board boots to U-boot with the same UBL and u-boot from the DVSDK 2.1. However, the EMAC no longer works with the PHY. My assumption was that this made sense because the clocking was probably messed up due to using the same PLL multiplies and divides for the 300MHz. So I went into UBL, changed the numbers to match the specs in section 3 of the main datasheet, and recompiled. Still no EMAC. Can anyone give me any help or things to look at. I will post the relevant UBL code later when I get to that computer.

Also I have seen some stuff about a patch that fixes a compatiblity issue with a V2 DM365 EMAC??

http://www.mail-archive.com/u-boot@lists.denx.de/msg26690.html

This code seems to be a different u-boot branch than the one that came with the 2.10 DVSDK so I don't think I can patch it with this. Is there an issue with a V2 EMAC IP and u-boot?

Help is greatly appreciated.

Kevin

0 Kevin Claycomb over 15 years ago in reply to Kevin Claycomb

Intellectual 420 points

Here is a cut form my UBL mods..

***PLL1

PLL1->PLLM   =   0x12;   // VCO will 24*2M/N+1 = 432Mhz
PLL1->PREDIV =   0x8001;

PLL1->SECCTL = 0x00470000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
    // for(j=0; j<0x100; j++) {}
    PLL1->SECCTL = 0x00460000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
// for(j=0; j<0x100; j++) {}
    PLL1->SECCTL = 0x00400000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
// for(j=0; j<0x100; j++) {}
    PLL1->SECCTL = 0x00410000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1

     //Program the PostDiv for PLL1
     PLL1->POSTDIV = 0x8000;

     // Post divider setting for PLL1

     PLL1->PLLDIV2 = 0x8001;
     PLL1->PLLDIV3 = 0x8001;   // POST DIV 432/2 -> 216 MJCP/HDVICP
     PLL1->PLLDIV4 = 0x8003;   // POST DIV 432/4 -> 108 EDMA/EDMA CFG
     PLL1->PLLDIV5 = 0x8001;   // POST DIV 432/2 -> 216 VPSS
     PLL1->PLLDIV6 = 0x8011;   //

        PLL1->PLLDIV7 = 0x8000;   // POST DIV 432/2 -> DDR has internal /2 so 216 MHz
     PLL1->PLLDIV8 = 0x8003;   // POST DIV 432/4 -> 108 MMC0/SD0
     PLL1->PLLDIV9 = 0x8001;   // POST DIV 432/2 -> 216 CLKOUT

******PLL2

PLL2->PLLM = 0x5A; // VCO will 24*2M/N+1 = 540Mhz
PLL2->PREDIV = 0x8007;

PLL2->POSTDIV = 0x8000;

PLL2->SECCTL = 0x00470000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
     PLL2->SECCTL = 0x00460000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
     PLL2->SECCTL = 0x00400000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
     PLL2->SECCTL = 0x00410000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1

   // Post divider setting for PLL2

     PLL2->PLLDIV2 = 0x8001;   // 540/2 =270 Mhz -> ARM
PLL2->PLLDIV4 = 0x8019;   // POST DIV 540/26 = 20.8 -> VOICE
PLL2->PLLDIV5 = 0x8007;   // POST DIV 594/8 = 77 ->VIDEO HD *** not needed

****

Kevin

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DM365 PLL initialization in the boot process