ECC Validation and Verification

PhilM5

Hi All,

Some short questions :

- How could it be made possible to generate ECC errors on the DDR3 in Software ? (to trigger a fault so to test efficiency of the controller)

- If ECC is invalidated does it also inhibit the writes to the ECC DDRAM or only the ECC controller during a read ?

Thanks & Regards

Phil

over 10 years ago

0 Rahul Prabhu over 10 years ago

TI__Guru** 116170 points

Hi Phil,

ECC feature on DDR3 controller on K2 devices can be tested at uboot level using a special commands "ddr ecc_err" and "ecc_test". .Please refer to the following MCSDK wiki article provided below to see how to simulate ECC error on DDR3 to test ECC feature on the DDR3 controller

http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Exploring#DDR3_ECC

ECC is used to protect the integrity of the the data stored on the DDR so errors are typically detected during reads. If there is a ECC corruption/generation error during writes, the DDR3 controller will generate a write ECC error interrupt but will allow the write to go through, it would be detected as ECC error during read. Please refer to the ECC section of the DDR3 controller for details:

http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf

Regards,

Rahul

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ECC Validation and Verification