• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 566 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ak66h smartreflex

Moshe Lerner
Prodigy 100 points
Other Parts Discussed in Thread: UCD74120, UCD9224

Hello

 

We are developing a data acquisition board using 66AK2HAAAW24 DSPs. As described in the K2 datasheet, there is only one SmartReflex (SR) interface on the following pins: AT39, AR37, AR36, AT38, AU38, AR35.

In the schematics drawings of the evaluation board "K2H_K2EVM-HK_SCH_A104_REV3_0.DSN" there are two SR interfaces, one for DSP and another one for ARM where it is defined at reserved pins: AU36, AV37, AU37, AV36, AU35, AW36.

There is no any information on the SR interface for the ARM in the documentation of the K2.

The question is if we can use the a fixed power for the ARM core, as defined in the HW design guide, or we need implement the SR circuit?

 

Regards

 

Moshe Lerner

  • 0
    TI__Mastermind 42545 points

    Hi Moshe,

    Originally, the support for separate SmartReflex interfaces for the DSP and ARM cores was included to facilitate a best-case power solution. During testing of the device, we found that using a separate reflex supply did not reduce the power enough to justify it. Consequently the core supplies were combined as CVDD in the data manual. There is no solution for a K2H design with separate supplies for DSP and ARM. What document did you see that in?

    Regards, Bill 

  • 0 in reply to Bill Taboada
    Prodigy 100 points

    Hi Bill

    Thanks for your answer.

    I sow the separate supplies in the schematics  of evaluation board "K2H_K2EVM-HK_SCH_A104_REV3_0.DSN". There are two VID interfaces VCNT0 to VCNT5 and VCNT0T to VCNT5T on page page 21 of the schematics. These interfaces are connected to the UCD9224 (page 40). The two UCD74120 are working in current sharing mode and it requires the VID codes from both interfaces be equal. So there is no need to connect second VID to the power controller. Is it right?

    Regards

  • 0 in reply to Moshe Lerner
    TI__Mastermind 42545 points

    Hi Moshe,

    Connecting the second VID interface is not needed. The two UCD74125 power stage components are both controlled by  the digital pulse width monitor output DPWM1A and are slaved to the first VID control interface. The EVM was designed before the decision was made to combine the CVDD and CVDDT core voltages. Rather than redesigning the power supply circuit, the power stage parts were connected in parallel to a single controller. Please note that in the data manual, the CVDDT pins have been changed to CVDD. 

    Regards, Bill