C6713 IPD/IPU resistor state during Internal Reset

Hi,

Team is working on this and will provide an update on this.

Thanks & regards,

Sivaraj K

Hi Sivaraj K,

Thank you for your reply.

I have another question. In the case of power-on reset, when is the IPD/IPU resistor on each terminal valid after C6713 is powered-up?

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

Hi Titus S,

Thank you for your reply.

The reference shown by you mentions the conditions before a hardware-reset after a power-up. I understand that all IPD/IPU resistors are at an uncertain state before the RESET is held low after a power-up, and they should be at the states as described in the datasheet after a hardware-reset sequence is completed if the RESET is held low during power-up. Are all IPD/IPU resistors at an uncertain state while the internal reset is held low?

Best regards,
 
Daisuke

Hi Titus S,
 
Sorry for taking your precious time.
 
I understand that all IPD/IPU resistors are at an uncertain state while the internal reset is held low. Is my understanding correct?
 
Best regards,
 
Daisuke

Hi Senthil,

Thank you for your reply.

Do you explain the case that the RESET is pulled low after the supply voltages and the clock input are at their proper operating conditions?

If the RESET is held low during power-up, when do the IPD/IPU resistors come to a known default state? Is it not defined?

Best regards,

Daisuke

Hi Senthil,

Thank you for your reply.

Best regards,

Daisuke