Hi,
I am trying to benchmark the EDMA performance on transferring data across LL2 <-> DDR, LL2 <-> MSMC, MSMC <-> DDR. I am encountering a discrepancy on EDMA throughput between the values described in "sprabh2a.pdf" and my measured values.
The environment that I use:
- platform: C6678 EVM (TMDSEVM6678LE)
- initialize DDR3 with the TI provided default GEL file for 1333MHz
- C6678 is set to run at 1GHz
- elapse Time computed with hardware timer 8 (setup according to datasheet)
- transfer rate equation in MBps: dataSizeInKBytes * 1GHz / (elapseTime * 6 * 1024)
- initialize EDMA transfer as per the CSL EDMA example in the following steps:
1. CSL_edma3Init
2. CSL_edma3Open (using CC1)
3. CSL_edma3HwControl (DMAREGION_ENABLE, using shadow region 2)
4. CSL_edma3HwControl (INTR_ENABLE, enabling interrupt for shadow region 2)
4. CSL_edma3HwChannelOpen (opening channel 0)
5. CSL_edma3HwChannelSetupQue (mapping channel 0 to TC0 queue of CC1)
- trigger EDMA transfer as per the CSL EDMA example in the following steps:
1. CSL_edma3MapDMAChannelToParamBlock (with the OPT, SRC, ACnt, BCnt, etc. setup)
2. CSL_edma3GetParamHandle (to get the handle)
3. CSL_edma3ParamSetup (to write the setup to PARAM)
4. CSL_edam3DMAChannelEnable (to enable the channel)
5. CSL_edma3SetDMAChannelEvent (to tribber event)
- wait for the EDMA tranfer to finish by polling the interrupt bit, using the following CSL call:
CSL_edma3HwControl (QUERY_INTRPEND)
- After that resetting the channel:
1. CSL_edma3HwControl (INTERPEND_CLEAR)
2. CSL_edma3ClearDMACHannelEvent
3. CSL_edma3DMAChannelDisable
I am expecting my result would be close to what it published in Table 15 of sprabh2a.pdf for DDR-LL2 transfer (theoretical thruput: 10664MBPS, aggregate thruput: 10132.3 MBPS), but I am getting less than half of it between DDR & LL2 transfer, and worse between LL2 & MSMC in which cases the published values are much better. Let me provide some of my test result for your reference:
------ LL2 to DDR Test:
LL2 to DDR 8MB transfer elapse Time: 1604.142000 us; Transfer rate = 4987.089672 MBps
LL2 to DDR 1MB transfer elapse Time: 208.914000 us; Transfer rate = 4786.658625 MBps
LL2 to DDR 100KB transfer elapse Time: 22.128000 us; Transfer rate = 4413.243312 MBps
LL2 to DDR 32KB transfer elapse Time: 8.466000 us; Transfer rate = 3691.235530 MBps
------ DDR to LL2 Test:
DDR to LL2 100KB transfer elapse Time: 22.500000 us; Transfer rate = 4340.277689 MBps
------ MSMC to LL2 Test:
MSMC to LL2 100KB transfer elapse Time: 22.506000 us; Transfer rate = 4339.120590 MBps
------ LL2 to MSMC Test:
MSMC to SL2 100KB transfer elapse Time: 22.530000 us; Transfer rate = 4334.498358 MBps
(FYI, an extra note: I have preformed similar EDMA throughput benchmarking on C6472. It's similar setup and I could get pretty close to theoretical throughput value for C6472 EDMA transfer.)
Can anyone let me know what could the source of the problem may be? Any initialization problem? Anything I might have missed, and/or anything I should pay attention to?
Thanks,
-- Louis
