vector.asm

Where do you find this file?   SYS/BIOS and TI-RTOS examples do not include such a file.

Thanks,
-Karl-

i have copied a vector.asm file . is it an interrupt vector table? if so how do we branch to a particular "INTx" from the main assembly code?

.ref _timer0_isr
.ref _qdma_isr
.ref _c_int00


.sect "vectors"
RESET_RST:

mvkl .S2 _c_int00, B0
mvkh .S2 _c_int00, B0
B .S2 B0
NOP
NOP
NOP
NOP
NOP
NMI_RST:
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

RESV1:
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

RESV2:
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT4: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT5: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT6: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT7: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT8: b _qdma_isr
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT9: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT10: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT11: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT12: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT13: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT14: b _timer0_isr
NOP
NOP
NOP
NOP
NOP
NOP
NOP

INT15: NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP

Thanking you

Ranjana,

we can't help if you won't provide us some context. We're not familiar as to what product might be shipping this vector.asm. Please state what TI product you're using.

ok...am sorry.. i forgot to mention about that

am using TMS320C6701 device and am coding in assembly in CCS3.3v. I wanted to interrupt the CPU via TIMER0 interrupt hence i configured all the registers needed and all the interrupt enable bits in registers were also set. 

When i read few documents  it was known that vector.asm is an interrupt vector table. But i cant understand how should we branch to this vector file (specifically 1C0 location INT14) from the main assembly code??How can i write my desired ISR in the 1C0h th location

Thanks  a ton for all the help

I don't think that this is the correct place for this question.  This is the TI-RTOS forum for posts related to an OS.  Are you using DSP/BIOS?  

Ranjana,

I went ahead and moved this thread over to the device forum in hopes that you will get a faster response to your question there.

oh..ok...no am not using DSP/BIOS

Thank you..

You should look at how StarterWare implements vectors. In that code, each interrupt vector will save registers, branch to a C code handler and restore the registers. See intvecs.asm and interrupt.c.

Your code is an interrupt table. Each interrupt consists of 8 instructions. There are 3 branches defined.
RESET_RST -> _c_int00
INT8 -> b _qdma_isr
INT14 -> b _timer0_isr
The vector code is placed at proper location for the vector table by the linker command file.

first of all ...thankyou for your reply..but my doubt still remains....

When i set all the registers the program must route to INT14(xxxxx1C0h) in  vector.asm right?  how do i fix the locations from 00h to 1e0h only for interrupts and their ISRs? 

Just noticed you are using the C6701. My experience is with the C674x processors. Some guesses based upon the documentation (spra544d.pdf). Not sure what you are asking. Your code has a ".sect "vectors"". You should have an link command file (eg. lnk.cmd) that contains instructions to place the section "vectors". The document spra544d.pdf has this example.

MEMORY
{
VECS: o = 00000000h l = 00000200h
}
SECTIONS
{
vectors : load=CE1VECS, run=VECS
}

Ranjana,

The TI C6000 DSPs are very capable, even the older ones like the C6701. Many customers find very valuable uses in many industries and applications, and you will end up with a fine finished program when you have completed this design you are working on.

Programming these DSPs is not as simple as walking up to a PC and running a java compiler and writing code to run on a PC. These are embedded processors that can be finely tuned for optimum performance, and they do come with a powerful set of compiler tools, assembly language tools, and debug tools.

But it is not possible to just grab anyone's file, write a program and then ask us on the forum why it does not work. The vectors.asm file that you show is not a valid vector table file. The only thing it will do well is handle the reset vector, and that will only happen if it is linked at the right address of 0x00000000 using the method shown above by Norman.

You have some reading and studying to do before you will be able to program and use this device. Fortunately, we have the documents you will need and especially the training material that you need, and these are all made available online for you.

The place to start is to go through the entire C6000 Integration Workshop (IW6000). Do the labs and follow the slides and Student Guide. There is no way that we can post all of this to you on the forum, so this is the way that you can get the information you need to understand how to get started. You can go to the TI Wiki Pages and search for C6000 training, and look for the C6x1x workshop, or click the link I gave you above.

Most of the technical documents you need will be found in the TMS320C6701 Product Folder technical documents section, here. For example, you will find an application note about the vector table and boot ROM creation that may be helpful.

Of particular interest will be the TMS320C6000 Assembly Language Tools User's Guide, but be sure to find the revision that covers the version of tools that you are using.

Also, the TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide will have information on the use of interrupts and how these relate to the vector table and the ISTP register.

These documents will be more valuable to read, in my opinion, after you have been through the archived C6000 training material I mentioned first. You will learn about the Chip Support Library (CSL) and will see examples of using the vector table and a real example of a vectors assembly file.

Regards,
RandyP

RANJANA AJAYAKUMAR said:

When i read few documents  it was known that vector.asm is an interrupt vector table. But i cant understand how should we branch to this vector file (specifically 1C0 location INT14) from the main assembly code??How can i write my desired ISR in the 1C0h th location

You don't branch to the vector table.  That happens automatically in the hardware.  I suggest that you read some more on interrupts in the CPU and Instruction Set Guide.  In particular the ISTP register points to the base of the vector table and there's a specific formatting expected by the CPU (i.e. one fetch packet per interrupt).