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csi2 complexio reset issue

selvam mk
Intellectual 970 points

Other Parts Discussed in Thread: DM385

Hi All,

We are trying to integrate 1 lane MIPI camera sensor to DM385 MIPI interface. problem is csi2 complexio cfg never comes out of reset ( value of cfg register is 4b000021).

Can anyone tell me what could be the reason  for this ?

Regards,

Manoj

  • 0
    TI__Guru**** 170625 points

    Hi Manoj,

    Are you using IPNC RDK?

    See if the below e2e threads will be in help:

    http://e2e.ti.com/support/omap/f/849/p/265581/929326.aspx#929326

    http://e2e.ti.com/support/omap/f/849/t/270773.aspx

    http://e2e.ti.com/support/omap/f/849/t/233645.aspx

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 120 points

    I had this same problem in two different occasions, you may be interested in #2 below.

    #1:

    CSI2_COMPLEXIO_CFG did not come out of reset. I was able to make it come out of reset when I met the following two conditions:

    A) The camera is actually connected to the board (and sending data).

    B) I actually followed the ISS CSI2 PHY and Link initialization sequence. In particular the pull-down and pull-up resistors. For me the CSI2_COMPLEXIO_CFG came out of reset during this sequence right after I engaged the pull-up resistors. As a secondary note, the forcerxmode changed from 1 to 0 (after the related timer has expired) and then the complexio came out of reset. Again, this all happened right after the pull-ups were enabled.

    #2:
    At this point I had everything working pretty well when the issue came up again. Everything from #1 was still true and it took me a while to figure out why the CSI2_COMPLEXIO_CFG did not come out of reset anymore. I eventually figured out that bit 18 of CONTROL_CAMERA_RX (CTRLCLK) has somehow become a 0, when previously it had always been a 1. Now I explicitly make sure it is set to 1 and everything is working again.

    One thing you can check out that might indicate this problem is looking at REGISTER1, bits 28 and 29.

    While the issue was going on both BYTECLK and CAM_PHY_CTRL_FCLK were not provided. Once the issue was resolved both were provided.

    Good luck...

  • 0 in reply to Peter Gibbons18
    Intellectual 920 points

    Dear Peter

    I have same problem like "CSI2_COMPLEXIO_CFG did not come out of reset"

    Reading your comment, how can i access the pull up/down control register.

    DM385 has PINCNTL0 to 270 register to select pin multiplexing, but there is no option for MIPI CSI2 pad.

    Thanks in advance

    Hennessy

  • 0 in reply to Hennessy
    TI__Guru**** 170625 points
    Hi Hennessy,

    I think Peter refer to DM38x ISS user's guide, section 2.3.2.2 ISS CSI2 PHY and Link Initialization Sequence

    www.ti.com/.../spruhl6a.pdf

    pull up/down example settings:

    CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[8] CSI21_DX4_INPUTENABLE = 0x1

    CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[8] CSI21_DX3_INPUTENABLE = 0x1

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 645 points
    Hey Pavel,

    I'm unable to find anymore information about the pull up/down registers. I do see there is a reference to CONTROL_CAMERA_RX register in the TRM at 3.2.43 but this doesn't seem to contain the settings you mention above.

    Do you know the address for these registers and where I may find a description of them?

    Thanks
  • 0 in reply to Mikael Nelson
    TI__Guru**** 170625 points
    Mikael,

    See DM83x TRM (link below), search for registers CONTROL_CAMERA_RX and PINCTRL

    www.ti.com/.../spruhg1b.pdf

    See also DM38x DM (link below), search for PINCNTL registers (correspond to PINCTRL from TRM).

    www.ti.com/.../dm385.pdf

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 645 points
    Pavel,

    I wonder if you could elaborate a little more on this. In the TRM's CONTROL_CAMERA_RX section, the pull up/down bits are all labeled something like:

    ADDON3Y_PIPU_CTRL
    ADDON3X_PIPD_CTRL
    COREXB_PIPU_CTRL

    While the Image subsystem document describes the pull up/down values as:

    CONTROL_CORE_PAD0_CSI21_DX4_PAD1_CSI21_DY4[8] CSI21_DX4_INPUTENABLE = 0x1
    CONTROL_CORE_PAD0_CSI21_DX3_PAD1_CSI21_DY3[8] CSI21_DX3_INPUTENABLE = 0x1


    I don't see any other reference to the ADDON or CORE bits in the TRM, so I'm not sure how they relate to the values you mentioned in the ISS.

    Could you explain the correlation? Also, if I wanted to enable the pullups, which bits would I need to set?

    Thanks!
  • 0 in reply to Mikael Nelson
    TI__Guru**** 170625 points
    I will notify IPNC team, hope they will be able to elaborate more.

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Intellectual 645 points

    Pavel,

    Figure 19 in 2.3.1 shows the relationship between the Core and Addon lanes. The datasheet really makes you hunt to figure out the associations. 

    Thanks!