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Memory latency with parity/ECC of KeyStoneII devices

Michi Yama
Guru 10030 points

Hi,

I have one question regarding Memory latency.

According to some information,  ARM CorePac internal memory's latency is the below.

Core-L1: 4cycle access(3cycle latency)

Core-L2 : 20 cycle access(19cycle latency)

Core-L3(MSMC SRAM):　<50cycle

As you know, KeystoneII devices have Parity for L1/ECC for L2 internal memory.

Is the above cycle number(latency) included parity/ECC enabled?

In other words, does parity/ECC function influence to memory access(latency)?

Please advise me.

I appreciate your quick reply.

Best regards,

Michi 

  • 0
    TI__Mastermind 30825 points

    Michi,

    On the ARM some of this is ECC (l2 and MSMC) and some is Parity (L1) there's a short wiki covering this http://processors.wiki.ti.com/index.php/Keystone_Error_Detection_and_Correction_EDC_ECC.

    The latency is the same with or without Parity or ECC enabled.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Guru 10030 points

    Dear Chad-san,

    Thank you for your reply.

    I have one more question.

    As you know, I know the latency of L1/L2 for KeyStone device by TMS320C66x DSP Cache User Guide(sprugy8).

    But I don't know the latency of L3 memory (MSMC SRAM). Do you know it?

    I appreciate your quick reply.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    Guru 10030 points

    Dear Chad-san,

    Thank you for your support.

    I have one more question.

    You said "The latency is the same with or without Parity or ECC enabled." Is this applied for C66x Core?

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Mastermind 30825 points

    Michi-san,

    The statement is applicable to both the ARM CorePac and the C66x CorePac.  The ECC and Parity Functions for both the ARM and C66x do not add any extra latency beyond what is inherent in the data path.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Guru 10030 points

    Dear Chad-san,

    Thank you for your support.

    your quick reply is very helpful for me.

    Please give me C66x information of L3 memory (MSMC SRAM).

    I really appreciate your reply.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Mastermind 30825 points

    Michi-san,

    I apologize for the delay.  I'm trying to make sure I've got the correct information.  The Keystone II performance guide hasn't been published yet.  Based on internal testing the following are the latencies for C66x CorePac on Keystone II MSMC.

    When configured as a L2 the MSMC has 20 Cycle Latency for C66x CorePac, and if configured as an L3 it has 25 Cycle Latency.

    Best Regards,

    Chad