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Question about the CSL_GPTExample in c55_csl_3.04

Hi


I found an problem about the CSL_GPTExample in c55_csl_3.04 when it was tested on 5515ezDSP. Although the example runs very well without any modification of the original code, there 's an error in TIMER COUNT RATE VERIFICATION TEST if I moved the main fuction from csl_gpt_example.c to a new file named main.c. The wrong output of console is
TIMER COUNT RATE VERIFICATION TEST!
THIS TEST VERIFIES WHETHER THE TIMER IS RUNNING AT CONFIGURED RATE OR NOT
CPU clock is running at 100007KHz
Timer Prescaler Divide Value is Set to Divide by 4
GPT Runs at Rate 1/4 of the CPU System Clock
GPT Count is Initialized to 1/4 of CPU Clock Cycles per Millisecond
With Reference to CPU Clock GPT Will Take 1 Millisecond to Count Down the Timer to 0
So The CPU Should Execute Approximately 100007( Clock Cycles From the Starting of the Timer Till the Expiry of the Timer
GPT Open Successful
GPT Reset Successful
GPT Config Successful
GPT Stop Successful
Timer Count Reached Zero
NUMBER OF CPU CYCLES EXECUTED AFTER STARTING THE TIMER TILL THE TIMER EXPIRY: 92328
GPT IS NOT RUNNING AT THE CONFIGURED RATE!
TIMER COUNT RATE VERIFICATION TEST FAILED!!


The right output of console is
TIMER COUNT RATE VERIFICATION TEST!
THIS TEST VERIFIES WHETHER THE TIMER IS RUNNING AT CONFIGURED RATE OR NOT
CPU clock is running at 100007KHz
Timer Prescaler Divide Value is Set to Divide by 4
GPT Runs at Rate 1/4 of the CPU System Clock
GPT Count is Initialized to 1/4 of CPU Clock Cycles per Millisecond
With Reference to CPU Clock GPT Will Take 1 Millisecond to Count Down the Timer to 0
So The CPU Should Execute Approximately 100007( Clock Cycles From the Starting of the Timer Till the Expiry of the Timer
GPT Open Successful
GPT Reset Successful
GPT Config Successful
GPT Stop Successful
Timer Count Reached Zero
NUMBER OF CPU CYCLES EXECUTED AFTER STARTING THE TIMER TILL THE TIMER EXPIRY: 100020
GPT IS RUNNING AT THE CONFIGURED RATE!
TIMER COUNT RATE VERIFICATION TEST PASSED!!


Can anyone tell me why this happened and how to correct the error? Thanks.

  • Hi,

    Team will work on this and will let you know the update as soon as possible.

    Thanks & regards,

    Sivaraj K

  • Hi,

    The reason it failed might be due to the environment change (the main function got moved to a different file), due to this change the while loop which loops until the interrupt occurs becomes more efficient. Since CpuCycleCount is just an estimation, this counted just less than expected CPU clocks cycles when Interrupt occured. This could be the reason for causing such error. 

    The CSL example is just to illustrate the timer count down and Interrupt generation features. If you have requirement to exactly count the CPU cycle count then suggest you to take other efficient approaches.

    Hope the above information helps.

    Regards

     Vasanth