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DDR3(4xMT41J128M16) problem with DM8148

jerry lee
Prodigy 40 points

Hello all

We have developed two custom boards based on dm8148. The first one use 8 MT41J128M8JP-125, programmed with u-boot-04.04.00.02 ,it work very well. The second board use 4  MT41J128M16-125. We modified the macro define about the DDR3 in gel file DM814x_PG2.x.gel as follow:

 

#define    DDR_FREQ           800

//DDR3 400 MHz - CL=6,CWL=5

#define DDR3_EMIF_TIM1_DEFINE_400                  0x0AAAE4E3

#define DDR3_EMIF_TIM2_DEFINE_400                  0x202F7FDA

#define DDR3_EMIF_TIM3_DEFINE_400                  0x507F83FF

#define DDR3_EMIF_REF_CTRL_DEFINE2_400                    0x00000C30

#define DDR3_EMIF_SDRAM_CONFIG_DEFINE_400            0x61C012B2

#define DDR3_EMIF_DDRPHYCR_DEFINE_400                     0x00070209

 

#define DDR3_EMIF_SDRAM_ZQCR_DEFINE                 0x50074BE1

 

All the parameters were calculated by DM814x_DDR_Controller_Register_Configuration_spreadsheet_v1.0.xlsx

 

Then use BB_021_DDR3_TEST.out to test the DDR3. Data should be written into DDR3 are as follow:

 

but the actual data read out from DDR3 are very strange. Datas in memory brower window of CCS show as below:

The first data is 0xFFFFFFFD, but when I changed the base address of memory brower window ,the data value did not changed.

 

What’s wrong ? Maybe software (slave ratio) leveling?

Please help, thanks.

  • 0
    Prodigy 40 points

    use DM814x_DDR_Controller_Register_Configuration_spreadsheet_v1.0.xlsx to calculate

  • 0 in reply to jerry lee
    Prodigy 40 points

    I check my designs, including schematic and PCB layout. I did not find any problem.

    4 pieces of MT41J128M16-125, 2 for DM8148 DDR0 interface, and 2 for DM8148 DDR1 interface. 

    DM8148 DDR0 interface control bus topology is

    The actual length of pcb layout are :

    The length of DDR0_CLK0 (differential pair): A1+A2 is 1841.393 MILs, A3 is 580.2965 MILs. The length difference between the other clock/address/control bus signals and DDR0_CLK0 is below 10MILs.

     

    The length of Byte1(Data[0~7]) is between 1560 MILs to 1570 MILs, the length of DDR0_DQS0 is 1567.8758 MILs.

    The length of Byte2(Data[8~15]) is between 1258 MILs to 1268 MILs, the length of DDR0_DQS1 is 1267.6483 MILs.

    The length of Byte3(Data[16~23]) is between 1170 MILs to 1180 MILs, the length of DDR0_DQS2  is 1176.2937 MILs.

    The length of Byte4(Data[24~31]) is between 1110 MILs to 1120 MILs, the length of DDR0_DQS3 is  1116.6585 MILs.

     

    According to the file TI814x-DDR3-Init-U-Boot Wordwise SWleveling, I use tool RatioSeed_TI814x.xls to calculate the ratio values.

    Modify the register configuration value in Gel file TI814x_ddr3.gel, and run DDR3_SlaveRatio_ByteWiseSearch_TI814x.out, but failed.

    *********************************************************

           Byte level Slave Ratio Search Program Values 

    *********************************************************

                         BYTE3   BYTE2   BYTE1   BYTE0

    *********************************************************

    Read DQS MAX          0    0    0    0

    Read DQS MIN           0    0    0    0

    Read DQS OPT          0    0    0    0

    *********************************************************

    Read DQS GATE MAX       0     0    0    0

    Read DQS GATE MIN 0     0    0    0

    Read DQS GATE OPT       0     0    0    0

    *********************************************************

    Write DQS MAX          0    0    0    0

    Write DQS MIN           0    0    0    0

    Write DQS OPT          0    0    0    0

    *********************************************************

    Write DATA MAX         0    0    0    0

    Write DATA MIN          0    0    0    0

    Write DATA OPT         0    0    0    0

     

  • 0 in reply to jerry lee
    TI__Guru**** 170625 points

    Hi Jerry,

    Please see if the below e2e threads will be in help:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/120664.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/297157.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/272030/956249.aspx#956249

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/136893.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/233504.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/180437.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/218073.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/160592.aspx

    http://e2e.ti.com/support/arm/sitara_arm/f/791/t/371209.aspx

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 40 points

    Hi, Pavel

    I changed the DDR3 frequency to 300MHz,  and changed the register configurations same to  TI814x_ddr3.gel

    //DDR3 300 MHz - CL=5,CWL=5
    #define DDR3_EMIF_TIM1_DEFINE_300 0x0888A394
    #define DDR3_EMIF_TIM2_DEFINE_300 0x20237FE2
    #define DDR3_EMIF_TIM3_DEFINE_300 0x501F820F
    #define DDR3_EMIF_REF_CTRL_DEFINE2_300 0x00000924
    #define DDR3_EMIF_SDRAM_CONFIG_DEFINE_300 0x61C009B2
    #define DDR3_EMIF_DDRPHYCR_DEFINE_300 0x00170208

    And I test it in CCS, it appeared to read error either.

    Thanks

    Jerry Lee

  • 0 in reply to jerry lee
    TI__Guru**** 170625 points

    Jerry,

    jerry lee said:
    //DDR3 300 MHz - CL=5,CWL=5
    #define DDR3_EMIF_TIM1_DEFINE_300 0x0888A394
    #define DDR3_EMIF_TIM2_DEFINE_300 0x20237FE2
    #define DDR3_EMIF_TIM3_DEFINE_300 0x501F820F
    #define DDR3_EMIF_REF_CTRL_DEFINE2_300 0x00000924
    #define DDR3_EMIF_SDRAM_CONFIG_DEFINE_300 0x61C009B2
    #define DDR3_EMIF_DDRPHYCR_DEFINE_300 0x00170208

    These DDR3 300MHz settings seems to be valid for the DM814x EVM DDR3 chips, while you have other DDR3 chips in your custom board. These values should be specific for your custom board depending on the external DDR3 chips you are using.

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/327038/1139944.aspx#1139944

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/327038/1142358.aspx#1142358

    Can you also run the mtest check:

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init#Run_mtest

    Regards,
    Pavel