This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
I am using the AIF2 module on C6670 DSP, with LTE FDD , CPRI mode .
The AIF2 LLD is easy for me to config the entire AIF2 registers, but without support of the LTE EXTENDED SYMBOL mode. Is there any sample code that show me how to set the extended symbol mode ?
/****************************************************************************\
* Copyright (C) 2009 Texas Instruments Incorporated. *
* All Rights Reserved *
* *
* GENERAL DISCLAIMER *
* ------------------ *
* All software and related documentation is provided "AS IS" and without *
* warranty or support of any kind and Texas Instruments expressly disclaims*
* all other warranties, express or implied, including, but not limited to, *
* the implied warranties of merchantability and fitness for a particular *
* purpose. Under no circumstances shall Texas Instruments be liable for *
* any incidental, special or consequential damages that result from the *
* use or inability to use the software or related documentation, even if *
* Texas Instruments has been advised of the liability. *
****************************************************************************
* *
* Written by : *
* Albert Bae *
* Texas Instruments *
* 04 May, 2010 * *
* *
***************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <c6x.h>
#include <ti/csl/src/intc/csl_intc.h>
#include "Aif2_config.h"
#include "psc_util.h"
/* Define queues for common FDQs */
#define MONO_TX_COMPLETE_Q 2000
#define MONO_RX_FDQ 2001
/* These are for the AIF test */
#define MONO_RX_Q 900
#define MONO_TX_Q 512
//Users should use 16 bytes aligned data for Aif2 and PktDMA test
#pragma DATA_SECTION(mono_region,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_ALIGN (mono_region, 16)
Uint8 mono_region[1024 * 10256];//payload size is 10K bytes for extended cyclic prefix 20 MHz LTE
Uint32 EE_linkB_Raw[500];
Uint32 EgressEOP[500];
Uint32 IngressEOP[500];
/* Intc variable declarartion */
CSL_IntcObj intcObj;
CSL_IntcHandle hIntc;
CSL_IntcEventHandlerRecord EventHandler[8];
CSL_IntcGlobalEnableState state;
/* Global structures and variables */
CSL_Aif2Obj Aif2Obj;// Aif2 CSL object
CSL_Aif2Handle hAif2;// Aif2 handle
Bool ctrlArg; // Ctrl Argument;
CSL_Aif2Context Aif2Context;//Aif2 context
CSL_Aif2Param aif2Param;//AIF2 module specific parameters
CSL_Status status; // CSL status
CSL_Aif2Setup aif2Setup;//Aif2 HW setup
CSL_Aif2LinkSetup linkSetup[4];// Setup for links
CSL_Aif2GlobalSetup globalSetup;// global config for AIF2
CSL_Aif2CommonSetup commonSetup; // Setup for common params
#pragma DATA_SECTION(SdCommonSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(PdCommonSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(PeCommonSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(IngrDbSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(EgrDbSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(AdCommonSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(AtCommonSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(PhyTimerTc,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(RadTimerTc,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(PhyTimerInit,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(RadTimerInit,".extData_sect")//use DDR3 memory for test mode
CSL_Aif2SdCommonSetup SdCommonSetup;//SERDES common setup
CSL_Aif2PdCommonSetup PdCommonSetup;//PD common setup
CSL_Aif2PeCommonSetup PeCommonSetup;//PE common setup
CSL_Aif2IngrDbSetup IngrDbSetup;// Ingress data buffer setup
CSL_Aif2EgrDbSetup EgrDbSetup;// Egress data buffer setup
CSL_Aif2AdCommonSetup AdCommonSetup;// Aif2 DMA common setup
CSL_Aif2AtCommonSetup AtCommonSetup; // Aif2 Timer common setup
CSL_Aif2AtEventSetup AtEventSetup; // Aif2 Timer external and internal event setup
CSL_Aif2AtCountObj PhyTimerTc;// AT Phy Terminal Count setup
CSL_Aif2AtCountObj RadTimerTc;// AT Rad Terminal Count setup
CSL_Aif2AtCountObj PhyTimerInit;// AT Phy Init value setup
CSL_Aif2AtCountObj RadTimerInit;// AT Rad Init value setup
#pragma DATA_SECTION(ComLinkSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(SdLinkSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(RmLinkSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(TmLinkSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(PdLinkSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(PeLinkSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(RtLinkSetup,".extData_sect")//use DDR3 memory for test mode
#pragma DATA_SECTION(AtLinkSetup,".extData_sect")//use DDR3 memory for test mode
CSL_Aif2CommonLinkSetup ComLinkSetup[4]; // Aif2 link common setup
CSL_Aif2SdLinkSetup SdLinkSetup[4]; //SERDES link setup
CSL_Aif2RmLinkSetup RmLinkSetup[4]; //RM link setup
CSL_Aif2TmLinkSetup TmLinkSetup[4]; //TM link setup
CSL_Aif2PdLinkSetup PdLinkSetup[4]; //PD link setup
CSL_Aif2PeLinkSetup PeLinkSetup[4]; //PE link setup
CSL_Aif2RtLinkSetup RtLinkSetup[4]; //RT link setup
CSL_Aif2AtLinkSetup AtLinkSetup[4]; // Aif2 timer link setup (Pi, Delta, PE signal)
volatile unsigned int int4_result = 0, Symbol = 0;
interrupt void int4_isr(){
int i, chan;
Uint32 *temp;
Uint32 rx_count, tmp;
if(int4_result >= 9){
for(i = 0 ; i< 12;i++){
for(chan = 0; chan < 8; chan++){
tmp = pop_queue(MONO_TX_COMPLETE_Q);
tmp &= 0xFFFFFFF0;//set DESC_SIZE field to zero
temp = (Uint32 *)(tmp + MNAV_MONO_PACKET_SIZE);
temp[0] = (Uint32)(0x00008000 + chan + (Symbol << 7));//add symbol number into PS field
tmp |= 0x00000003;//set DESC_SIZE to 3 for AIF2 mono mode
push_queue((MONO_TX_Q + chan), 1, 0, tmp);
}
Symbol++;
if(Symbol == 120)Symbol = 0;
}
}
if(int4_result >= 10){
for(chan =0; chan < 8; chan++){
rx_count = get_descriptor_count((MONO_RX_Q + chan));
for (i = 0; i < rx_count; i ++)
{
tmp = pop_queue((MONO_RX_Q + chan));
tmp &= 0xFFFFFFF0;// clean DESC_SIZE field
push_queue(MONO_RX_FDQ, 1, 0, tmp);//recycling Rx descriptor
}
}
}
//EE_linkB_Raw[int4_result] = hAif2->regs->EE_LK[0].EE_LK_IRS_B;
//EgressEOP[int4_result] = hAif2->regs->DB_EDB_EOP_CNT;
//IngressEOP[int4_result] = hAif2->regs->AD_ISCH_EOP_CNT;
int4_result++;
}
void Intc_config(void)
{
CSL_IntcParam vectId;
CSL_IntcContext context;
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
//! GEM0 Intc Configuration !//
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!//
/* Setup the global Interrupt */
context.numEvtEntries = 8;
context.eventhandlerRecord = EventHandler;
CSL_intcInit(&context);
/* Enable NMIs */
CSL_intcGlobalNmiEnable();
/* Enable Global Interrupts */
CSL_intcGlobalEnable(&state);
/* VectorID for the Global Edma Event */
vectId = CSL_INTC_VECTID_4;
/* Opening a handle for the Fsync->EDMA Interrupt Event */
hIntc = CSL_intcOpen(&intcObj,
AIF2_EVENT2_INTSEL_MAP, // Event2
&vectId,
NULL);
//Hook the ISRs
CSL_intcHookIsr(vectId, &int4_isr);
// Clear the Interrupt
CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTCLEAR, NULL);
//Enable the Event & the interrupt
CSL_intcHwControl(hIntc, CSL_INTC_CMD_EVTENABLE, NULL);
}
void MNavigator_config(void)
{
Uint32 flow_a;
Uint32 flow_d;
Uint16 idx;
MNAV_MonolithicPacketDescriptor *mono_pkt;
/* Setup Memory Region 0 for 512 * 10256B Monolithic descriptors. Our
* Mono descriptors will be 12 bytes plus 4 bytes protocol specific field, plus
* 10240 bytes of payload(symbol). so the total size is 10256 bytes and it is dividable by 16
* 512 descriptors. (dead space is possible) */
set_memory_region(0, (Uint32) mono_region, 0, 0x02800005);
/*****************************************************************
* Configure Linking RAM 0 for the descriptor regions.
*/
set_link_ram(0, QM_LRAM_REGION, 0x3fff); //internal link ram
/* Initialize descriptor regions to zero */
memset(mono_region, 0, 1024 * 10256);
/* Push 192 Monolithic packets into Tx Completion Queue */
for (idx = 0; idx < 512; idx ++)
{
mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 10256));
mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
mono_pkt->data_offset = 16;
mono_pkt->pkt_return_qmgr = 0;
mono_pkt->pkt_return_qnum = MONO_TX_COMPLETE_Q;
push_queue(MONO_TX_COMPLETE_Q, 1, 0, (Uint32)(mono_pkt));
}
/* Push 192 Monolithic packets to Rx FDQ */
for (idx = 512; idx < 1024; idx ++)
{
mono_pkt = (MNAV_MonolithicPacketDescriptor *)(mono_region + (idx * 10256));
mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
mono_pkt->data_offset = 16;
push_queue(MONO_RX_FDQ, 1, 0, (Uint32)(mono_pkt));
}
/*****************************************************************
* Configure Rx channel flows
*/
/* Note that when LOOPBACK_MODE is enabled, the PKTDMA will force
* force the flow ID value in the Tx Streaming I/F to be equal to
* the channel number. (normally, the Tx flow ID is set to 0xff).
* This is a simulator special testing feature. */
//Create flow configuration for the Monolithic packets
for(idx =0; idx < 8; idx++){
flow_a = 0x28100000 | (MONO_RX_Q + idx);
flow_d = MONO_RX_FDQ << 16;
config_rx_flow(AIF_PKTDMA_RX_FLOW_REGION, idx,
flow_a, 0, 0, flow_d, 0, 0, 0, 0);
}
/*****************************************************************
* Enable Tx and Rx channels.
*/
enable_disable_loopback(0);//disable PKTDMA loopback for normal data transfer
for(idx =0; idx < 8; idx++){
config_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, idx, 0x01000000); //set AIF_MONO_MODE to 1 and set PS filter to zero
enable_tx_chan(AIF_PKTDMA_TX_CHAN_REGION, idx, 0x80000000);
enable_rx_chan(AIF_PKTDMA_RX_CHAN_REGION, idx, 0x80000000);
}
}
void Aif2_MNAV_Cpri_config(void)
{
int i, j;
/************ Initialize Aif2 structures to avoid unwanted configuration ************************************************/
memset(&globalSetup, 0, sizeof(globalSetup));
for(i=0;i<4;i++)
memset(&linkSetup[i], 0, sizeof(linkSetup));
memset(&commonSetup, 0, sizeof(commonSetup));
memset(&SdCommonSetup, 0, sizeof(SdCommonSetup));
memset(&PdCommonSetup, 0, sizeof(PdCommonSetup));
memset(&PeCommonSetup, 0, sizeof(PeCommonSetup));
memset(&IngrDbSetup, 0, sizeof(IngrDbSetup));
memset(&EgrDbSetup, 0, sizeof(EgrDbSetup));
memset(&AdCommonSetup, 0, sizeof(AdCommonSetup));
memset(&AtCommonSetup, 0, sizeof(AtCommonSetup));
memset(&AtEventSetup, 0, sizeof(AtEventSetup));
memset(&PhyTimerInit, 0, sizeof(PhyTimerInit));
memset(&RadTimerInit, 0, sizeof(RadTimerInit));
memset(&PhyTimerTc, 0, sizeof(PhyTimerTc));
memset(&RadTimerTc, 0, sizeof(RadTimerTc));
for(i=0;i<4;i++){
memset(&ComLinkSetup[i], 0, sizeof(ComLinkSetup));
memset(&SdLinkSetup[i], 0, sizeof(SdLinkSetup));
memset(&RmLinkSetup[i], 0, sizeof(RmLinkSetup));
memset(&TmLinkSetup[i], 0, sizeof(TmLinkSetup));
memset(&PdLinkSetup[i], 0, sizeof(PdLinkSetup));
memset(&PeLinkSetup[i], 0, sizeof(PeLinkSetup));
memset(&RtLinkSetup[i], 0, sizeof(RtLinkSetup));
memset(&AtLinkSetup[i], 0, sizeof(AtLinkSetup));
}
// Initialize CSL library, this step is required
CSL_aif2Init(&Aif2Context);
// Open Aif2 and get handle
hAif2 = CSL_aif2Open(&Aif2Obj, CSL_AIF, &aif2Param, &status);
if ((hAif2 == NULL) || (status != CSL_SOK))
{
printf ("\nError opening CSL_AIF2");
exit(1);
}
/************** populating AIF2 major setup structures ***************************************************/
aif2Setup.globalSetup = &globalSetup;
aif2Setup.commonSetup = &commonSetup;
aif2Setup.linkSetup[CSL_AIF2_LINK_0] = &linkSetup[0];
aif2Setup.linkSetup[CSL_AIF2_LINK_1] = &linkSetup[1];
aif2Setup.linkSetup[CSL_AIF2_LINK_2] = &linkSetup[2];
aif2Setup.linkSetup[CSL_AIF2_LINK_3] = &linkSetup[3];
// populate global config fields
globalSetup.ActiveLink[CSL_AIF2_LINK_0] = TRUE;
globalSetup.ActiveLink[CSL_AIF2_LINK_1] = TRUE;
globalSetup.ActiveLink[CSL_AIF2_LINK_2] = TRUE;
globalSetup.ActiveLink[CSL_AIF2_LINK_3] = TRUE;
globalSetup.frameMode = CSL_AIF2_FRAME_MODE_NORMAL;
//populate common config fields
commonSetup.pSdCommonSetup = &SdCommonSetup;
commonSetup.pPdCommonSetup = &PdCommonSetup;
commonSetup.pPeCommonSetup = &PeCommonSetup;
commonSetup.pIngrDbSetup = &IngrDbSetup;
commonSetup.pEgrDbSetup = &EgrDbSetup;
commonSetup.pAdCommonSetup = &AdCommonSetup;
commonSetup.pAtCommonSetup = &AtCommonSetup;
commonSetup.pAtEventSetup = &AtEventSetup;
/****Link Setup (Do this setup repeatedly with different link setup structure if user wants to use multiple links) ***/
//populate link config fields for 6 links
for(i=0;i<4;i++){
linkSetup[i].linkIndex = (CSL_Aif2LinkIndex)(CSL_AIF2_LINK_0 + i);
linkSetup[i].pComLinkSetup = &ComLinkSetup[i];
linkSetup[i].pSdLinkSetup = &SdLinkSetup[i];
linkSetup[i].pRmLinkSetup = &RmLinkSetup[i];
linkSetup[i].pTmLinkSetup = &TmLinkSetup[i];
linkSetup[i].pPdLinkSetup = &PdLinkSetup[i];
linkSetup[i].pPeLinkSetup = &PeLinkSetup[i];
linkSetup[i].pRtLinkSetup = &RtLinkSetup[i];
linkSetup[i].pAtLinkSetup = &AtLinkSetup[i];
//Link Common setup
ComLinkSetup[i].linkProtocol = CSL_AIF2_LINK_PROTOCOL_CPRI;
ComLinkSetup[i].linkRate = CSL_AIF2_LINK_RATE_4x;
ComLinkSetup[i].IngrDataWidth = CSL_AIF2_DATA_WIDTH_15_BIT;
ComLinkSetup[i].EgrDataWidth = CSL_AIF2_DATA_WIDTH_15_BIT;
//SD link setup
SdLinkSetup[i].rxAlign = CSL_AIF2_SD_RX_COMMA_ALIGNMENT_ENABLE;
SdLinkSetup[i].rxLos = CSL_AIF2_SD_RX_LOS_ENABLE;
SdLinkSetup[i].rxCdrAlgorithm = CSL_AIF2_SD_RX_CDR_FIRST_ORDER_THRESH_1;
SdLinkSetup[i].rxInvertPolarity = CSL_AIF2_SD_RX_NORMAL_POLARITY;
SdLinkSetup[i].rxTermination = CSL_AIF2_SD_RX_TERM_COMMON_POINT_0_7 ;//for AC coupled application
SdLinkSetup[i].rxEqualizerConfig = CSL_AIF2_SD_RX_EQ_ADAPTIVE;//Equalizer On
SdLinkSetup[i].bRxEqHold = FALSE;//fixed value
SdLinkSetup[i].bRxOffsetComp = TRUE;//fixed value
SdLinkSetup[i].bEnableTxSyncMater = TRUE; //fixed value
SdLinkSetup[i].txInvertPolarity = CSL_AIF2_SD_TX_PAIR_NORMAL_POLARITY;
SdLinkSetup[i].txOutputSwing = CSL_AIF2_SD_TX_OUTPUT_SWING_14;
SdLinkSetup[i].txPrecursorTapWeight = CSL_AIF2_SD_TX_PRE_TAP_WEIGHT_2;// -5%
SdLinkSetup[i].txPostcursorTapWeight = CSL_AIF2_SD_TX_POST_TAP_WEIGHT_24;// -20%
SdLinkSetup[i].bTxFirFilterUpdate = TRUE;//FIR filter update on
//TM link setup
TmLinkSetup[i].bEnableTmLink = TRUE;
TmLinkSetup[i].bEnableRmLos = FALSE;
TmLinkSetup[i].SeedValue = 0x1;
TmLinkSetup[i].bEnableScrambler = FALSE;
TmLinkSetup[i].pCpriTmSetup.L1InbandEn = 0;//disable 9 bits mask
TmLinkSetup[i].pCpriTmSetup.RmLinkLosError = CSL_AIF2_LINK_0;//select link 0 as source RM link
TmLinkSetup[i].pCpriTmSetup.RmLinkLofError = CSL_AIF2_LINK_0;//select link 0 as source RM link
TmLinkSetup[i].pCpriTmSetup.RmLinkLosRx = CSL_AIF2_LINK_0;//select link 0 as source RM link
TmLinkSetup[i].pCpriTmSetup.RmLinkLofRx = CSL_AIF2_LINK_0;//select link 0 as source RM link
TmLinkSetup[i].pCpriTmSetup.RmLinkRaiRx = CSL_AIF2_LINK_0;//select link 0 as source RM link
TmLinkSetup[i].pCpriTmSetup.TxStartup = 0;
TmLinkSetup[i].pCpriTmSetup.TxPointerP = 20;
TmLinkSetup[i].pCpriTmSetup.TxProtocolVer = 1;
//RM link setup
RmLinkSetup[i].bEnableRmLink = TRUE;
RmLinkSetup[i].RmFifoThold = CSL_AIF2_RM_FIFO_THOLD_IMMEDIATELY;
RmLinkSetup[i].RmErrorSuppress = CSL_AIF2_RM_ERROR_ALLOW;
RmLinkSetup[i].bEnableSdAutoAlign = FALSE;
RmLinkSetup[i].bEnableScrambler = FALSE;
RmLinkSetup[i].bEnableLcvUnsync = FALSE;
RmLinkSetup[i].bEnableLcvControl = FALSE;
RmLinkSetup[i].bEnableWatchDog = FALSE;
RmLinkSetup[i].WatchDogWrap = 0xFF;//set watch dog wrap value
RmLinkSetup[i].bEnableClockQuality = FALSE;
RmLinkSetup[i].ClockMonitorWrap = 0;//disabled
RmLinkSetup[i].losDetThreshold = RM_LOS_DET_THOLD;
RmLinkSetup[i].SyncThreshold = RM_SYNC_THOLD;
RmLinkSetup[i].FrameSyncThreshold = RM_SYNC_THOLD;
RmLinkSetup[i].UnsyncThreshold = RM_UNSYNC_THOLD;
RmLinkSetup[i].FrameUnsyncThreshold = RM_UNSYNC_THOLD;
//RT link setup
RtLinkSetup[i].CiSelect = CSL_AIF2_LINK_0;
RtLinkSetup[i].bEnableEmptyMsg = TRUE;
RtLinkSetup[i].RtConfig = CSL_AIF2_RT_MODE_TRANSMIT;// takes PE input only
//PD link setup
PdLinkSetup[i].bEnablePdLink = TRUE;
PdLinkSetup[i].CpriEnetStrip = 0;//disable ethernet strip for control channel
PdLinkSetup[i].Crc8Poly = CRC8_POLY;
PdLinkSetup[i].Crc8Seed = CRC8_SEED;
PdLinkSetup[i].CpriCwNullDelimitor = 0xFB;//K 27.7 charactor
PdLinkSetup[i].CpriCwPktDelimitor[0] = CSL_AIF2_CW_DELIM_NULLDELM;//4
PdLinkSetup[i].PdCpriCrcType[0] = CSL_AIF2_CRC_16BIT;
PdLinkSetup[i].bEnableCpriCrc[0] = TRUE;//enable CPRI CRC for control channel 0
PdLinkSetup[i].PdPackDmaCh[0] = 124;//Set DB channel 124 as a dma ch for control channel 0
PdLinkSetup[i].bEnablePack[0] = FALSE;//disable CPRI control channel 0 packing
PdLinkSetup[i].PdCpriDualBitMap.DbmX = 1;// set X-1
PdLinkSetup[i].PdCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample
PdLinkSetup[i].PdCpriDualBitMap.Dbm1Mult = 0;//set n-1
PdLinkSetup[i].PdCpriDualBitMap.Dbm1Size = 0;//set n-1
PdLinkSetup[i].PdCpriDualBitMap.Dbm1Map[0] = 0x0;
PdLinkSetup[i].PdCpriDualBitMap.Dbm2Size = 0;
PdLinkSetup[i].PdCpriDualBitMap.Dbm2Map[0] = 0x0;
PdLinkSetup[i].CpriDmaCh[0]= (i*2); //match DbmX channel 0 to DB channel i
PdLinkSetup[i].bEnableCpriX[0]= TRUE; //enable CPRI X channel 0
PdLinkSetup[i].bEnableCpriPkt[0]= FALSE;//use AxC data for X channel 0
PdLinkSetup[i].Cpri8WordOffset[0]= 0;//Word level CPRI data offset for X channel 0
PdLinkSetup[i].CpriDmaCh[1]= ((i*2)+ 1); //match DbmX channel 0 to DB channel i+1
PdLinkSetup[i].bEnableCpriX[1]= TRUE; //enable CPRI X channel 0
PdLinkSetup[i].bEnableCpriPkt[1]= FALSE;//use AxC data for X channel 0
PdLinkSetup[i].Cpri8WordOffset[1]= 0;//Word level CPRI data offset for X channel 0
for(j=0;j<256;j++)//cpri cw lut setup
{
PdLinkSetup[i].CpriCwChannel[j]= 0; //set cw channel num to pack 0
PdLinkSetup[i].bEnableCpriCw[j]= TRUE; //enable CPRI CW sub channel
}
//PE link setup
PeLinkSetup[i].bEnablePeLink = TRUE;
PeLinkSetup[i].PeCppiDioSel = CSL_AIF2_CPPI;
PeLinkSetup[i].TddAxc = FALSE;
PeLinkSetup[i].PeDelay = DB_PE_DELAY_CPRI;//0 sys_clks delay between DB and PE
PeLinkSetup[i].Crc8Poly = CRC8_POLY;
PeLinkSetup[i].Crc8Seed = CRC8_SEED;
PeLinkSetup[i].PeCpriDualBitMap.DbmX = 1;//set X-1
PeLinkSetup[i].PeCpriDualBitMap.DbmXBubble = 1;//2 bubbles of 1 AxC sample
PeLinkSetup[i].PeCpriDualBitMap.Dbm1Mult = 0;//set n-1
PeLinkSetup[i].PeCpriDualBitMap.Dbm1Size = 0;//set n-1
PeLinkSetup[i].PeCpriDualBitMap.Dbm1Map[0] = 0x0;
PeLinkSetup[i].PeCpriDualBitMap.Dbm2Size = 0;
PeLinkSetup[i].PeCpriDualBitMap.Dbm2Map[0] = 0x0;
PeLinkSetup[i].CpriAxCPack = CSL_AIF2_CPRI_15BIT_SAMPLE;
PeLinkSetup[i].CpriCwNullDelimitor = 0xFB;//K 27.7 character
PeLinkSetup[i].CpriCwPktDelimitor[0] = CSL_AIF2_CW_DELIM_NULLDELM;
PeLinkSetup[i].PePackDmaCh[0] = 124;
PeLinkSetup[i].bEnablePack[0] = FALSE;
for(j=0;j<256;j++)//cpri cw lut setup
{
PeLinkSetup[i].CpriCwChannel[j]= 0; //set cw channel num to pack 0
PeLinkSetup[i].bEnableCpriCw[j]= TRUE; //enable CPRI CW sub channel
}
//AT link setup
AtLinkSetup[i].PE1Offset = 300;
AtLinkSetup[i].PE2Offset = 310;
AtLinkSetup[i].DeltaOffset = 380;
AtLinkSetup[i].PiMin = 380;
AtLinkSetup[i].PiMax = 400;
AtLinkSetup[i].IsNegativeDelta = FALSE;//positive delta
}
/************** Common Setup ********************************************************************************/
//SD common setup
SdCommonSetup.bEnablePllB8 = TRUE;
SdCommonSetup.CLKBYP_B8 = CSL_AIF2_PLL_CLOCK_NO_BYPASS;
SdCommonSetup.LB_B8 = CSL_AIF2_PLL_LOOP_BAND_MID;//High BW is also fine
SdCommonSetup.VoltRangeB8 = CSL_AIF2_PLL_VOLTAGE_LOW;//fixed factor
SdCommonSetup.SleepPllB8 = CSL_AIF2_PLL_AWAKE;
SdCommonSetup.pllMpyFactorB8 = CSL_AIF2_PLL_MUL_FACTOR_20X;//for CPRI when reference clock is 122.88 Mhz
SdCommonSetup.SysClockSelect = CSL_AIF2_SD_BYTECLOCK_FROM_B8;
//PD common setup
PdCommonSetup.PdCppiDioSel = CSL_AIF2_CPPI;//AxC data uses CPPI for DMA machine
PdCommonSetup.AxCOffsetWin = AXC_OFFSET_WIN;//AxC offset window
PdCommonSetup.PdRadtTC = 2457599;//Radio frame size for CPRI
PdCommonSetup.PdFrameTC[0].FrameIndexSc = 0;//start index
PdCommonSetup.PdFrameTC[0].FrameIndexTc = 0;//teminal index
PdCommonSetup.PdFrameTC[0].FrameSymbolTc = 119;//120 extended cyclic prefix symbols in one rad frame.
for(i=0;i<8;i++){//8 LTE channels
PdCommonSetup.PdChConfig[i].bChannelEn = TRUE;//Channel enable
PdCommonSetup.PdChConfig[i].DataFormat = CSL_AIF2_LINK_DATA_TYPE_NORMAL;//Data format
PdCommonSetup.AxCOffset[i] = 0;//this is the number of QW level data to skip
PdCommonSetup.PdChConfig1[i].DataFormat = CSL_AIF2_GSM_DATA_OTHER;//Non GSM data
PdCommonSetup.PdChConfig1[i].FrameCounter = 0;//CPRI framing counter group number
PdCommonSetup.PdChConfig1[i].TddEnable = 0xFFFF;//PD TDD, enables all symbols(FDD)
PdCommonSetup.TddEnable1[i] = 0xFFFFFFFF;//enables all symbols(FDD)
PdCommonSetup.TddEnable2[i] = 0xFFFFFFFF;//enables all symbols(FDD)
PdCommonSetup.TddEnable3[i] = 0xFFFFFFFF;//enables all symbols(FDD)
PdCommonSetup.TddEnable4[i] = 0xFFFFFFFF;//enables all symbols(FDD)
}
PdCommonSetup.PdFrameMsgTc[0] = 639;//Frame message terminal count for extended cyclic prefix symbol
//PE common setup
PeCommonSetup.PeTokenPhase = 0;//Phase alignment for scheduling DMA normally set to zero
PeCommonSetup.EnetHeaderSelect = 1;
PeCommonSetup.PeFrameTC[0].FrameIndexSc = 0;//start index
PeCommonSetup.PeFrameTC[0].FrameIndexTc = 0;//teminal index
PeCommonSetup.PeFrameTC[0].FrameSymbolTc = 119;//120 extended cyclic prefix symbols in one rad frame.
for(i=0;i<8;i++){//8 LTE channels
PeCommonSetup.bEnableCh[i] = TRUE;//Enable PE channel
PeCommonSetup.PeDmaCh0[i].bCrcEn = FALSE;//disable CRC
PeCommonSetup.PeDmaCh0[i].FrameTC = 0;//use framing terminal count 0
PeCommonSetup.PeDmaCh0[i].RtControl = CSL_AIF2_PE_RT_INSERT;//use PE insert option
PeCommonSetup.PeDmaCh0[i].CrcType = CSL_AIF2_CRC_8BIT;//CRC type
PeCommonSetup.PeDmaCh0[i].isEthernet = FALSE;//AxC data
PeCommonSetup.PeDmaCh0[i].CrcObsaiHeader = FALSE;
PeCommonSetup.PeInFifo[i].MFifoWmark = 3;//Message FIFO water mark
PeCommonSetup.PeInFifo[i].MFifoFullLevel = 5;//Message FIFO full level
PeCommonSetup.PeInFifo[i].SyncSymbol = 0;
PeCommonSetup.PeAxcOffset[i] = 310;// same to PE2 offset
}
PeCommonSetup.PeFrameMsgTc[0] = 2559;//Frame message terminal count for extended cyclic prefix symbol
//PE Channel LUT setup and link routing selection (ChIndex number is matched with link number)
PeCommonSetup.ChIndex0[0] = 0; //for link 0
PeCommonSetup.bEnableChIndex0[0] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn0[0] = FALSE; //for AxC
PeCommonSetup.ChIndex0[1] = 1; //for link 0
PeCommonSetup.bEnableChIndex0[1] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn0[1] = FALSE; //for AxC
PeCommonSetup.ChIndex1[0] = 2; //for link 1
PeCommonSetup.bEnableChIndex1[0] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn1[0] = FALSE; //for AxC
PeCommonSetup.ChIndex1[1] = 3; //for link 1
PeCommonSetup.bEnableChIndex1[1] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn1[1] = FALSE; //for AxC
PeCommonSetup.ChIndex2[0] = 4; //for link 2
PeCommonSetup.bEnableChIndex2[0] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn2[0] = FALSE; //for AxC
PeCommonSetup.ChIndex2[1] = 5; //for link 2
PeCommonSetup.bEnableChIndex2[1] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn2[1] = FALSE; //for AxC
PeCommonSetup.ChIndex3[0] = 6; //for link 3
PeCommonSetup.bEnableChIndex3[0] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn3[0] = FALSE; //for AxC
PeCommonSetup.ChIndex3[1] = 7; //for link 3
PeCommonSetup.bEnableChIndex3[1] = TRUE;//Route egress channel to dedicated CPRI link
PeCommonSetup.CpriPktEn3[1] = FALSE; //for AxC
//Ingress DB setup
IngrDbSetup.bEnableIngrDb = TRUE; //Enable Ingress DB
for(i=0;i<8;i++){//8 channels
IngrDbSetup.bEnableChannel[i] = TRUE; //Enable Ingress DB channel 0
IngrDbSetup.IngrDbChannel[i].BaseAddress = AIF2_DB_BASE_ADDR_I_FIFO_0 + (i*4); //Set DB FIFO base address
IngrDbSetup.IngrDbChannel[i].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW32; //Set DB FIFO depth to 32 QW(Quad word)
IngrDbSetup.IngrDbChannel[i].DataSwap = CSL_AIF2_DB_NO_SWAP; //for DL
IngrDbSetup.IngrDbChannel[i].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
IngrDbSetup.IngrDbChannel[i].bEnablePsData = TRUE; //Enable 4 bytes PS data
IngrDbSetup.IngrDbChannel[i].PacketType = 0; //User data
}
//Egress DB setup
EgrDbSetup.bEnableEgrDb = TRUE; //Enable Ingress DB
EgrDbSetup.PmControl = CSL_AIF2_DB_AXC_TOKEN_FIFO;//to enhance CPRI performance
for(i=0;i<8;i++){//8 channels
EgrDbSetup.bEnableChannel[i] = TRUE; //Enable Egress DB channel 0
EgrDbSetup.EgrDbChannel[i].BaseAddress = AIF2_DB_BASE_ADDR_E_FIFO_0 + (i*4); //Set DB FIFO base address
EgrDbSetup.EgrDbChannel[i].BufDepth = CSL_AIF2_DB_FIFO_DEPTH_QW32; //Set DB FIFO depth to 32 QW
EgrDbSetup.EgrDbChannel[i].DataSwap = CSL_AIF2_DB_NO_SWAP; //for DL
EgrDbSetup.EgrDbChannel[i].IQOrder = CSL_AIF2_DB_IQ_NO_SWAP; //No Order change
}
//AD Common setup
AdCommonSetup.IngrGlobalEnable = TRUE;
AdCommonSetup.EgrGlobalEnable = TRUE;
AdCommonSetup.FailMode = CSL_AIF2_AD_DROP;//drop fail packet
AdCommonSetup.IngrPriority = CSL_AIF2_AD_PKT_PRI;
AdCommonSetup.EgrPriority = CSL_AIF2_AD_AXC_PRI;
AdCommonSetup.Tx_QueNum = AIF2_BASE_TX_QUE_NUM;//base egress queue number setup to 512
//AT Common setup
AtCommonSetup.PhySyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Phy timer trigger
AtCommonSetup.RadSyncSel = CSL_AIF2_SW_SYNC;//Select SW sync for Rad timer trigger
AtCommonSetup.SyncMode = CSL_AIF2_NON_RP1_MODE;
AtCommonSetup.AutoResyncMode = CSL_AIF2_AUTO_RESYNC_MODE;
AtCommonSetup.CrcMode = CSL_AIF2_AT_CRC_DONT_USE;//Do not use RP1 CRC in this test
AtCommonSetup.PhytCompValue = 0;
AtCommonSetup.AtInit.pPhyTimerInit = &PhyTimerInit;
AtCommonSetup.AtInit.pRadTimerInit = &RadTimerInit;
PhyTimerInit.ClockNum = 0;
PhyTimerInit.FrameLsbNum = 0;
PhyTimerInit.FrameMsbNum = 0;
RadTimerInit.ClockNum = 0;
RadTimerInit.SymbolNum = 0;
RadTimerInit.FrameLsbNum = 0;
RadTimerInit.FrameMsbNum = 0;
AtCommonSetup.AtTerminalCount.pPhyTimerTc = &PhyTimerTc;
AtCommonSetup.AtTerminalCount.pRadTimerTc = &RadTimerTc;
PhyTimerTc.FrameLsbNum = FRAME_COUNT_TC_PHY_TIMER;//set phy Frame TC to 4095
PhyTimerTc.ClockNum = CLOCK_COUNT_TC_PHY_TIMER_CPRI; //set phy clock TC for CPRI
RadTimerTc.FrameLsbNum = FRAME_COUNT_TC_LTE_FDD;//set LTE Frame TC to 4095
RadTimerTc.SymbolNum = SYMBOL_COUNT_TC_LTE_FDD; //set LTE Symbol TC to 9 (sub frame time)
RadTimerTc.LutIndexNum = 0; //set LTE lut index TC to zero
AtCommonSetup.AtTerminalCount.RadClockCountTc[0] = CLOCK_COUNT_TC_LTE_FDD_CPRI;//set LTE Clock count TC forCPRI
//AT Event setup (Event 2)
AtEventSetup.AtRadEvent[2].EventSelect = CSL_AIF2_EVENT_2;//Select Event 2
AtEventSetup.AtRadEvent[2].EventOffset = 0;
AtEventSetup.AtRadEvent[2].EvtStrobeSel = CSL_AIF2_RADT_SYMBOL;
AtEventSetup.AtRadEvent[2].EventModulo = 245759;//LTE 1ms sub-frame time
AtEventSetup.AtRadEvent[2].EventMaskLsb = 0xFFFFFFFF;
AtEventSetup.AtRadEvent[2].EventMaskMsb = 0xFFFFFFFF;
AtEventSetup.bEnableRadEvent[2] = TRUE;//Enable Event 2
/****** Do AIF2 HW setup (set all MMRs above) **********************************************************************/
CSL_aif2HwSetup(hAif2, &aif2Setup);
ctrlArg = TRUE;
for(i=0;i<4;i++){
hAif2->arg_link = (CSL_Aif2LinkIndex)(CSL_AIF2_LINK_0+i);//Select link num
//Enable Serdes loopback
//CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_LINK_LOOPBACK, (void *)&ctrlArg);
//Enable Tx/Rx of link 0
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_TX_LINK, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_ENABLE_DISABLE_RX_LINK, (void *)&ctrlArg);
}
for(i=0;i<100;i++)asm (" NOP 9 ");//insert time delay for aif2 configuration complete
//AT Arm timer
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_ARM_TIMER, (void *)&ctrlArg);
//Trigger the SW debug frame sync
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DEBUG_SYNC, (void *)&ctrlArg);
}
void main(void)
{
Uint32 *temp;
Uint32 idx, idx2, tmp;
MNAV_MonolithicPacketDescriptor *mono_pkt;
//printf("Beginning AIF2 CPRI LTE 4x rate 4links power test:\n\n");
for(idx=0;idx<10000;idx++)asm (" NOP 9 ");//insert time delay for printf operation
enable_module(aif_pdctl, aif_mdctl);//Enable AIF2 module power
int4_result = 0;
Intc_config();
MNavigator_config();//multicore navigator configuration for LTE
for(idx =0; idx < 512; idx++){ //configure 256 free descriptors for infinite power test
tmp = pop_queue(MONO_TX_COMPLETE_Q);
tmp &= 0xFFFFFFF0;//set DESC_SIZE field to zero
mono_pkt = (MNAV_MonolithicPacketDescriptor *)tmp;
//Create Mono packet (initialize non-zero fields)
mono_pkt->type_id = MNAV_DESC_TYPE_MONO;
mono_pkt->data_offset = MNAV_MONO_PACKET_SIZE + 4;//16
mono_pkt->packet_length = 10240;
mono_pkt->ps_flags = 1;
mono_pkt->epib = 0;
mono_pkt->psv_word_count = 1; // 4 byte PS field length
mono_pkt->pkt_return_qnum = MONO_TX_COMPLETE_Q;
temp = (Uint32 *)(tmp + 16);
for (idx2 = 0; idx2 < 2560; idx2 ++) temp[idx2] = 0x2AAA2AAA; //power test data setup
push_queue(MONO_TX_COMPLETE_Q, 1, 0, tmp);
}
Aif2_MNAV_Cpri_config();//Aif2 configuration for M Navigator mode
/*****************************************************************
* Enable AIF and wait for completion.
*/
while(1)
{
asm (" NOP 9 ");
asm (" NOP 9 ");
if(int4_result == 10000)//wait 10 sec
{
//AT disable all events and halt timer
ctrlArg = TRUE;
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_DISABLE_ALL_EVENTS, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AT_HALT_TIMER, (void *)&ctrlArg);
ctrlArg = FALSE;//disable AD scheduler and Rx, Tx Link
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_E_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg);
CSL_aif2HwControl(hAif2, CSL_AIF2_CMD_AD_IN_ENABLE_DISABLE_GLOBAL, (void *)&ctrlArg);
CSL_aif2Reset(hAif2);//reset all aif2 modules
break;
}
}
printf("\nEnding AIF2 CPRI LTE 4x rate 4links power test\n");
}
Hi,
I'm not the person who creates LLD but I have one very low level (CSL-FL level) example code which use Extended symbol. Please use this code for your part of reference.
Regards,
Albert