DM8148 - PLL_DSP output through CLKOUT0

Padmanabhan KS

For our development testing using the custom board, we would like to measure PLL_DSP. For this, we intend to utilise the CLKOUT0 pin.

From the TRM, we understand that we need to tweak the CLKOUT_MUX register and set bits 3-0 as 0x0 [Source is PRCM_SYSCLK_OUT]. We identified PRCM_SYSCLK_OUT based on the CLKOUTx Source Selection Logic diagram from the datasheet as shown below.

But from the attached image, it seems like PRCM_SYSCLK_OUT is a muxed output of PLL_DSP, PLL_HDVICP, PLL_VIDEO0, PLL_AUDIO, and RTCDIVIDER.

How do we choose to output PLL_DSP only from above muxed options? Please correct us if i am missing something.

Regards,

Padmanabhan

over 10 years ago

0 Pavel Botev over 10 years ago

TI__Guru**** 170625 points

Padmanabhan,

Padmanabhan KS said:
From the TRM

This Figure 7-11 is from the DM814x datasheet (SPRS647E), not DM814x TRM (SPRUGZ8E).

Padmanabhan KS said:
How do we choose to output PLL_DSP only from above muxed options?

Your understanding for the CLKOUT_MUX register is correct, you should select [3:0] CLKOUT0_MUX = 0x0 to export the PRCM output clock signal to the CLKOUT0 pin.

The other register, which selects among the PRCM clock signals, is the CM_CLKOUT_CTRL. See DM814x TRM (SPRUGZ8E), section 2.3.11 Clock Output Pin and section 2.10.3.1 CM_CLKOUT_CTRL Register

In TRM, the bit you need is: CM_CLKOUT_CTRL[1:0] CLKOUTSOURCE = 0x1: DPLL_DSP_CLK : USB PLL clock output

It is actually not clear if the value of 0x1 is for DSP PLL or USB PLL.

While in linux kernel source code we have:

linux-2.6.37-psp04.04.00.01/arch/arm/mach-omap2/clock814x_data.c

/***************************** Clock Out Connection **************************/
static const struct clksel clkout0to3_mux_sel[] = {
   { .parent = &dsp_dpll_ck, .rates = div_1_0_rates },
   { .parent = &hdvicp_dpll_ck, .rates = div_1_1_rates },
   { .parent = &video0_dpll_ck, .rates = div_1_2_rates },
   { .parent = &rtc_divider_ck, .rates = div_1_3_rates },
   { .parent = NULL}
};

This means CM_CLKOUT_CTRL[1:0] CLKOUTSOURCE = 0x0 for DSP_PLL

I think that the linux kernel is the correct one, not the TRM. The DSP PLL output clock is 500MHz by default, so you should have this 500MHz value on the CLKOUT0 pin.

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/dsp_dpll_ck/gem_fck# cat rate
500000000

root@dm814x-evm:/sys/kernel/debug/clock/osc0_clkin_ck/dsp_dpll_ck/clkout_prcm_mux_ck/clkout_prcm_ck/sys_clkout1# cat rate
500000000

Regards,
Pavel

0 Padmanabhan KS over 10 years ago in reply to Pavel Botev

Intellectual 510 points

Hi Pavel

Thanks for your detailed response. I will check with our software team on this.

Another thing: Is there a method to output the arm cortex clock through CLK_OUT pins? I don't seem to find it in the datasheet or TRM.

Regards,

Padmanabhan

0 Pavel Botev over 10 years ago in reply to Padmanabhan KS

TI__Guru**** 170625 points

Padmanabhan,

Padmanabhan KS said:
Another thing: Is there a method to output the arm cortex clock through CLK_OUT pins? I don't seem to find it in the datasheet or TRM

No, Cortex-A8 ARM clock can not be exported to the clkout0/1 pins.

Regards,
Pavel

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DM8148 - PLL_DSP output through CLKOUT0