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Error in runing DIO Library testDIO_edmaStreamLsu.pjt



Configuration:

DIO Lib 1.0.0, CCSv3.3,  evmC6474, no BIOS, slave node is the testDIO_dbell_slave.pjt, master on core 1A, slave on core 2A

Hi

Occasionally when I re-start the testDIO_edamStreamLsu.pjt, I get the following output by the master

COM: Application error = 'SRIO INITIALIZATION'
COM: Source line = '768'
COM: User Info = '0x1'

And the slave is stuck in the for loop below (RIO_init.c).

RIO_waitForHw(Uint32 delay)
{
    volatile Uint32 i, n;
    n = 0;
    for (i = 0; i < delay; i++)
    {
        n = n + 1;
    }
}

Where the RIO_waitForHw() function is called from the huge function RIO_init() at

                RIO_waitForHw(100000);
                /* Check Port Ok bit */
                portNok = 0;
                   if ( srioHandle->portConfig == RIO_PORT_CONFIG_1X_4X_MODE) {
                    response.index = 0;
                    CSL_srioGetHwStatus (srioHandle->hCslObj, CSL_SRIO_QUERY_SP_ERR_STAT, &response);
                    portNok |= response.data;
                }else{
                    for (index=0; index< CSL_SRIO_MODULE_PORTS_MAX; index++) {
                       if (srioHandle->portEn[index]) {
                          response.index = index;
                          CSL_srioGetHwStatus (srioHandle->hCslObj, CSL_SRIO_QUERY_SP_ERR_STAT, &response);
                          portNok |= response.data;
                       }
                    }
                }


Anyone else seen this problem or have an idea how to debug/fix it?

Power cycles typically work, but not always.

Cheers

  • Thought I'd add the gel file since that may be the issue. (strange, I couldn't upload the .gel, but I could upload the zipped version)

    7635.evmc6474.zip

    Its the same one that came with the EVMC6474.

    Cheers

  • What I think it happening is the the slave is hung in DIO_waitForHw because the master has not configured the PSC properly for the SRIO domain. If the masters SRIO isn't active, the slave waits until it can start exchanging SRIO phy initialization packets (IDLE, configuration, etc.).

    You have to make sure to enable the SRIO Poser Sleep Controller (PSC) MDCLT register properly. The code below has solved the problem.

        //Next state is enable
        CSL_FINS(hPsc->regs->MDCTL6, PSC_MDCTL6_NEXT, CSL_PSC_MDCTL6_NEXT_ENABLE);

        //De-Assert local reset
        //CSL_FINS(hPsc->regs->MDCTL6, PSC_MDCTL6_LRSTZ, CSL_PSC_MDCTL6_LRSTZ_DE-ASSERTLOCALRESET);
        CSL_FINS(hPsc->regs->MDCTL6, PSC_MDCTL6_LRSTZ, 1);

        //Enable bit in appropriate power domain module
        CSL_FINS(hPsc->regs->PTCMD, PSC_PTCMD_G0,(0x00000001 << 0));

    I modified the code from the TSIP setup in the PSC user guide sprueg3b p21

    Cheers

     

  • WARNING!

    The post above is for a different DSP. I started the thread with the C6474 and switched to the different TI C64x+ DSP. .

    Cheers