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IPC global variable share problem on DSP6678

jian zong1
Intellectual 390 points

I find a IPC example project . in the project core0 triger ipc interrupt to core1.
and core1 trogers ipc interrupt to core2,and so on.i have no EVM board and this project is run under simulator mode.

I defined a glbal variable 'int g_flag = 3'.In the correspondig ipc_isr function, i added one to g_flag and
print its value in console.
however the output message is below , it looks as if the global variable added only once . it means the variable is not shared by all the eight cores.
how to define and use a global variable that can be operated by all cores on DSP6678 under IPC ?thanks.
Set interrupt from Core 0 to Core 1, cycle = 1053673622
Interrupt Info 0
[TMS320C66x_1] Receive interrupt from Core 0 with info 0x0, cycle = 1057016594
g_flag = 4
Set interrupt from Core 1 to Core 2, cycle = 1057033058
Interrupt Info 8
[TMS320C66x_2] Receive interrupt from Core 1 with info 0x0, cycle = 1059235265
g_flag = 4
Set interrupt from Core 2 to Core 3, cycle = 1059251792
Interrupt Info 16
[TMS320C66x_3] Receive interrupt from Core 2 with info 0x10, cycle = 1057523984
g_flag = 4
Set interrupt from Core 3 to Core 4, cycle = 1057540624
Interrupt Info 24
[TMS320C66x_4] Receive interrupt from Core 3 with info 0x10, cycle = 1060312891
g_flag = 4
Set interrupt from Core 4 to Core 5, cycle = 1060329531
Interrupt Info 32
[TMS320C66x_5] Receive interrupt from Core 4 with info 0x20, cycle = 1060791800
g_flag = 4
Set interrupt from Core 5 to Core 6, cycle = 1060808440
Interrupt Info 40
[TMS320C66x_6] Receive interrupt from Core 5 with info 0x20, cycle = 1066910801
g_flag = 4
Set interrupt from Core 6 to Core 7, cycle = 1066927441
Interrupt Info 48
[TMS320C66x_7] Receive interrupt from Core 6 with info 0x30, cycle = 1070451703
g_flag = 4
Set interrupt from Core 7 to Core 0, cycle = 1070468343
Interrupt Info 56
[TMS320C66x_0] Receive interrupt from Core 7 with info 0x30, cycle = 1065998385
g_flag = 4
IPC test passed!

  • 0
    TI__Mastermind 20790 points

    Hi,

    Is the test code provided by TI or your own?

    This E2E post will help you,

     http://e2e.ti.com/support/embedded/tirtos/f/355/p/123986/442780.aspx#442780

    http://e2e.ti.com/support/embedded/tirtos/f/355/p/143155/517519.aspx#517519

    http://e2e.ti.com/support/embedded/tirtos/f/355/p/134908/486315.aspx#486315

  • 0 in reply to Pubesh
    Intellectual 390 points

    Hi

    I modified the IPC example project and defined a global g_flag. i only set two ipc_isr function.

    core 0 first send a IPC inturrupt to core1 . Core1 will add 1 to the global and subsequently sends IPC inturrupt to core0.
    after core0 received the inturrupt form core1, it will add 2475.twoCoreExamp.rar1 to the global again .
    therefor, the global g_flag added twice , the nitial value is 2, the printed valus are 3 and 4 .
    However , the printing message is below . why core0 will ouput g_flag=3 instead of 4?
    how to fix this problem ? I has attached my project below. thank you .

  • 0 in reply to jian zong1
    Intellectual 390 points

    Hi

    I modified the IPC example project and defined a global g_flag. i only set two ipc_isr function.

    core 0 first send a IPC inturrupt to core1 . Core1 will add 1 to the global and subsequently sends IPC inturrupt to core0.
    after core0 received the inturrupt form core1, it will add 1 to the global again .
    therefor, the global g_flag added twice , the nitial value is 2, the printed valus are 3 and 4 .
    However , the printing message is below . why core0 will ouput g_flag=3 instead of 4?
    how to fix this problem ? I has attached my project here . thank you .

    [TMS320C66x_0] Set interrupt from Core 0 to Core 1, cycle = 15622 Interrupt Info 0
    [TMS320C66x_1] Receive interrupt from Core 0 with info 0x0, cycle = 687498
    Core1 output :g_flag = 3,address =c3e0000
    Set interrupt from Core 1 to Core 0, cycle = 709011
    Interrupt Info 8
    [TMS320C66x_0] Receive interrupt from Core 1 with info 0x0, cycle = 1131531
    core0:g_flag = 3, address =c3e0000
    IPC test passed!

    5810.twoCoreExamp.rar

  • 0 in reply to jian zong1
    TI__Mastermind 20790 points

    Hi,

    Your code seems ok, I could not find any issue. I do not know exactly where is the issue. If still not solve your issue, you can post at TI-RTOS forum. So that you can get fast response from the experts.

  • 0 in reply to Pubesh
    Intellectual 390 points

    my problem is essentiallly global variable sharing in MSMC. in my project i defined a gloabla variable in MSMC . and two cores added it respectively . so  eventually ,the total effect is : g_flag = gflag +2;

    but   when i run the project , the global variable  added  only once , it equal to g_flag = g_flag+1.

    someone told me  .cache coherence can resolve my prblem and  a simple method is setting MSMC non-cacheable.I found a MAR can set cacheability . but the MAR15 is read-only .my global is defined  in MSMC .how to make  MSMC non-cacheable? thank you 

  • 0 in reply to jian zong1
    Intellectual 390 points

    help ! how to set MSMC non-cacheable?

  • 0 in reply to jian zong1
    TI__Mastermind 20790 points

    Hi,

    MSMC SRAM can serve as a Shared Level 2 or Level 3 memory.
    Shared Level 2 memory:

    • The MSMC memory is cacheable by L1D and L1P caches
    • L2 will not cache requests to MSMC SRAM

    See this wiki will be useful,

    http://processors.wiki.ti.com/index.php/MemoryProtectionOnKeystoneDevices