Other Parts Discussed in Thread: DM3730
Sorry about posting in this forum, but I did not see an appropriate forum for this processor.
We have a new design based upon the DM3730. The boot pins are wired as follows:
Boot0-3: 1
Boot4: 0
Boot5-6: 1
This should provide a boot sequence of USB, UART3, MMC1, NAND.
Nothing is happening, so we hooked up a Segger JTAG emulator. Examining the CONTROL_STATUS register, we get the folowing:
J-Link>mem 480022f0 4
480022F0 = 2F 03 00 00
The 2F seems reversed from what we would expect, F2. The TRM does not define what the bit order is for these bits.
Could anybody shed some light on the meaning of the SYSBOOT field of the CONTROL_STATUS register?
