Hi All,
1. TI full support is required. I'm having tough time, please solve it ASAP.
2. Using TI Sitara SDK 7.0 linux 3.12 for AM33xx
3. After running applications for few seconds system completely slows down.
4. When slowdown happens,
CM_CLKMODE_DPLL_MPU register is set to 5, DPLL is in Idle Bypass Low Power Mode. Found using devmem2. All applications run slowly and idle task does not run as all the applications need CPU.
5. In normal operating mode, the CM_CLKMODE_DPLL_MPU register is set to 7, DPLL in Lock mode
6. It's found that ARM Cortex M3 power management firmware has code to alter CM_CLKMODE_DPLL_MPU.
7. Before and after processor slows down,
root@am335x-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
ondemand
root@am335x-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
300000
8. Also tried changing scaling_governor to performance but the problem was not solved.
9. I also want a patch which solves below problem,
with dpll mpu = 300MHz set in uboot, I get below kernel prints,
cpufreq_cpu0: failed to scale voltage up: -22
with dpll mpu = 800MHz,
cpufreq_cpu0: failed to scale voltage down: -22
Changing the frequency of the CPU clock requires changing the frequency of the PLL that is
supplying the CPU clock. To change the frequency of the PLL, the CPU
clock is temporarily reparented to another parent clock.
The clock frequency of this temporary parent clock could be much
higher than the clock frequency of the PLL at the time of
reparenting. Due to the temporary increase in the CPU clock speed,
the CPU (and any other components in the CPU clock domain such as
dividers, mux, etc.) have to to be operated at a higher voltage
level, called the safe voltage level.
I want a patch that adds optional support to temporarily switch to a safe voltage level during CPU
frequency transitions.
Regards,
Gangadhar
