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Query on C6670 PLL and Timer Clock Source

Sudarshan R
Expert 1240 points

Hi All,

I have a query on the C6670 PLL. If the PLL is not initialized in the device, what is the source of the clock for the CorePac and other peripherals? 

I get a weird result if I use the Timer module without initializing the PLL 1(main PLL). I had posted about this a year back but couldn't get the solution. And now, it has haunted back again. So, want to know the actual cause.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/266859/935455.aspx

Here it is about whats happening:

When I don't initialize the PLL and run the device on real-time, my timer results are slowed down by 8. In the sense, if I have configured the timer to interrupt after every 10 seconds, it is interrupting after every 10*8=80 seconds. But, if I run the device after initializing the PLL, I get the perfect timer results (i.e. interrupts every 10 secs).  So, what was the actual cause before? What is the source of the Timer module when PLL is not initialized? How is it that I'm getting the perfect result after PLL initialization.

Someone please give a strong answer. 

Regards,

Sud

  • 0
    TI__Mastermind 43660 points

    Hello Sudharsan,

    What is the input clock frequency you are using ?

    what is the SYSCLK1 frequency after PLL initialization ?

    After power ON, the PLL comes up in Bypass mode by default and it will be changed to PLL mode during PLL initialization. During bypass mode, the input clock is directly fed into the PLL dividers.

    For timers, the clock source is SYSCLK1 and it has a fixed ratio of 1. If your SYSCLK1 and input clock ratio is 8, your timer results will be supposed to slowed down by 8 before PLL initialization.

    Regards,

    Senthil

    The PLL comes up in Bypass mode by default on powering up the

  • 0
    TI__Mastermind 43660 points

    Hello Sudharsan,

    There are three clock sources available for timer module, and it is selected by the combination of CLKSRC_LO and TIEN_LO bits.

    One among the three clock sources is internal clock which is SYSCLK1. You can have an option to divide down this internal clock source by using CLKDIV bits in EMUMGT_CLKSPD register.

    As said earlier, before PLL initialization, the internal clock is same as the input clock source.

    Please refer the below user guide for more clarification on timer module.

    http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf

    Regards,

    Senthil