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[DM814x / DM8127] SDIO clock and data signal configuration

Hayden Kim
Genius 15580 points

User wants to reduce peak at edge of signal of SDIO clock and data.

Is there any register to control peak signal shape?

Or, is there any register to control current of SDIO clock/data signals?

If there is no such register, how to reduce the peak of edge of the signals?

 

Best regards,

Hayden

  • 0
    TI__Guru**** 170625 points

    Hi Hayden,

    Hayden Kim said:
    Is there any register to control peak signal shape?

    I made a search in the DM814x TRM, chapter MMC/SD/SDIO, but I can not find such register.

    Hayden Kim said:
    Or, is there any register to control current of SDIO clock/data signals?

    I found one register/bit that might be related, see MMCHS_CON[11] CTPL

    Hayden Kim said:
    If there is no such register, how to reduce the peak of edge of the signals?

    See if the below e2e thread will be in help:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/275860.aspx

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    TI__Guru**** 170625 points

    Hayden,

    I have feedback from our MMC/SD/SDIO expert:

    We do not have registers to change the output currents, but we do have PMIC to change the I/O and core voltages, though that is not an ideal solution to fix overshoot/ reflection the customer may be seeing.
     
    Can you follow up with customer on the following:
    1.       Would be great to have a scope shot of the issue the customer is observing w/ details on SDIO operating speed, scope/probe used, and probing location on a schematic or simple block diagram
    2.       Make sure the probe is properly grounded / Use a different GND point to see if the results changed
    3.       Depending on how the connections are made, they might want to add a small series resistor for impedance matching