Error 8b/10b srio

/* SRIO Driver Includes. */
#include <ti/drv/srio/srio_types.h>
#include <ti/drv/srio/include/listlib.h>
#include <ti/drv/srio/srio_drv.h>

/* CSL SRIO Functional Layer */
#include <ti/csl/csl_srio.h>
#include <ti/csl/csl_srioAux.h>
#include <ti/csl/csl_srioAuxPhyLayer.h>

/* CSL BootCfg Module */
#include <ti/csl/csl_bootcfg.h>
#include <ti/csl/csl_bootcfgAux.h>

/* CSL Chip Functional Layer */
#include <ti/csl/csl_chip.h>

/* CSL PSC Module */
#include <ti/csl/csl_pscAux.h>

/* QMSS Include */
#include <ti/drv/qmss/qmss_drv.h>
#include <stdio.h>
#include <ti/csl/csl_tsc.h>


/**********************************************************************
 ************************* LOCAL Definitions **************************
 **********************************************************************/

/* These are the GARBAGE queues which are used by the TXU to dump the 
 * descriptor if there is an error instead of recycling the descriptor
 * to the free queue. */
#define GARBAGE_LEN_QUEUE		    905
#define GARBAGE_TOUT_QUEUE		    906
#define GARBAGE_RETRY_QUEUE		    907
#define GARBAGE_TRANS_ERR_QUEUE	    908
#define GARBAGE_PROG_QUEUE		    909
#define GARBAGE_SSIZE_QUEUE		    910

/* SRIO Device Information
 * - 16 bit Device Identifier.
 * - 8 bit Device Identifier.
 * - Vendor Identifier. 
 * - Device Revision. */
#define DEVICE_VENDOR_ID            0x30
#define DEVICE_REVISION             0x0

/* SRIO Assembly Information
 * - Assembly Identifier
 * - Assembly Vendor Identifier. 
 * - Assembly Device Revision. 
 * - Assembly Extension Features */
#define DEVICE_ASSEMBLY_ID          0x0
#define DEVICE_ASSEMBLY_VENDOR_ID   0x30
#define DEVICE_ASSEMBLY_REVISION    0x0
#define DEVICE_ASSEMBLY_INFO        0x0100

#define DEVICE_ID1_16BIT			0xBEEF
#define DEVICE_ID1_8BIT				0xBE
/**********************************************************************
 ************************* Extern Definitions *************************
 **********************************************************************/

/** @addtogroup SRIO_DEVICE_API
 @{ */

/**
 *  @b Description
 *  @n  
 *      The function provides the initialization sequence for the SRIO IP
 *      block. This can be modified by customers for their application and
 *      configuration.
 *
 *  @retval
 *      Success     -   0
 *  @retval
 *      Error       -   <0
 */
#pragma CODE_SECTION(SrioDevice_init, ".text:SrioDevice_init");

int32_t SrioDevice_init (void)
{
    CSL_SrioHandle      hSrio;
	int32_t             i;
    SRIO_PE_FEATURES    peFeatures;
    SRIO_OP_CAR         opCar;
    Qmss_QueueHnd       queueHnd;
    uint8_t             isAllocated;
    uint32_t            gargbageQueue[] = { GARBAGE_LEN_QUEUE,  GARBAGE_TOUT_QUEUE,
                                            GARBAGE_RETRY_QUEUE,GARBAGE_TRANS_ERR_QUEUE,
                                            GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE };
    uint32_t			srioIDMask = 0xFFFF;
    uint32_t			srio_primary_ID = 0xBEEF;
    uint32_t			srio_secondary_ID = 0xAAAA;
    Uint8				bootCompleteFlag;
	uint32_t 			rxConfig = 0;
	uint32_t 			txConfig = 0;
	Uint8				port;

    char		statusText[4]="";
    uint64_t	tscTemp;

    //CSR: For VMIN settings
    SRIO_PLM_VMIN_EXPONENT vminExponentConfig;

    int32_t openQueueValues[16] = {0};

    /* Disable SRIO reset isolation */
    if (CSL_PSC_isModuleResetIsolationEnabled(CSL_PSC_LPSC_SRIO))
    	CSL_PSC_disableModuleResetIsolation(CSL_PSC_LPSC_SRIO);

    /* Reset SRIO module and wait for the reset to complete */
    CSL_PSC_setModuleLocalReset (CSL_PSC_LPSC_SRIO,PSC_MDLRST_ASSERTED);
    CSL_PSC_setModuleNextState (CSL_PSC_LPSC_SRIO,PSC_MODSTATE_ENABLE);
    printf ("Debug: Waiting for module reset...\n");
    while (!CSL_PSC_isModuleResetDone(CSL_PSC_LPSC_SRIO));
    printf ("Debug: Waiting for module local reset...\n");
    while (!CSL_PSC_isModuleLocalResetDone (CSL_PSC_LPSC_SRIO));

    /* Get the CSL SRIO Handle. */
    hSrio = CSL_SRIO_Open (0);
    if (hSrio == NULL)
        return -1;

    /* Enable reception of packets */
	hSrio->RIO_PCR = (hSrio->RIO_PCR & 0x7) | CSL_SRIO_RIO_PCR_RESTORE_MASK;

    /* Disable the SRIO Global block */
	CSL_SRIO_GlobalDisable (hSrio);

	/* Disable each of the individual SRIO blocks. */
	for(i = 0; i <= 9; i++)
		CSL_SRIO_DisableBlock (hSrio, i);

	/* Set boot complete to be 0; we are not done with the initialization. */
	CSL_SRIO_SetBootComplete (hSrio, 0);

    /* Set the sRIO shadow registers for 9/3/2/2 */
    CSL_SRIO_SetLSUShadowRegs (hSrio,0x19,0x19);

	/* Now enable the SRIO block and all the individual blocks also. */
	CSL_SRIO_GlobalEnable (hSrio);
	for (i = 0; i <= 9; i++)
		CSL_SRIO_EnableBlock (hSrio,i);

	/* Configure SRIO to operate in Normal mode. */
	CSL_SRIO_SetNormalMode (hSrio,0);
	CSL_SRIO_SetNormalMode (hSrio,1);
	CSL_SRIO_SetNormalMode (hSrio,2);
	CSL_SRIO_SetNormalMode (hSrio,3);


	/* Enable Automatic Priority Promotion of response packets. */
	CSL_SRIO_EnableAutomaticPriorityPromotion (hSrio);

	/* Set the SRIO Prescalar select to operate in the range of 44.7 to 89.5 */
	CSL_SRIO_SetPrescalarSelect (hSrio, 0);

    /* Unlock the Boot Configuration Kicker */
    CSL_BootCfgUnlockKicker ();

   	/* Set Pll setting for single speed of 5Gpbs */
    CSL_BootCfgSetSRIOSERDESConfigPLL (0x241);

    /* Loop around until the SERDES PLL is locked. */
    while (1)
    {
    	uint32_t    status;

    	/* Get the SRIO SERDES Status */
        CSL_BootCfgGetSRIOSERDESStatus (&status);
        if (status & 0x1)
        	break;
    }

   	/* Get boot complete flag setting */
    CSL_SRIO_GetBootComplete (hSrio, &bootCompleteFlag);

    if (bootCompleteFlag == 1)
    /* Set boot complete to be 0; to enable writing to the SRIO registers. */
    CSL_SRIO_SetBootComplete (hSrio, 0);

    /* Set rx/tx config values based on the lane rate specified */
    /* Tx and Rx settings for 5 Gbps */
    // (0)     Enable Receiver
    // (1-3)   Bus Width 010b (20 bit)
    // (4-5)   Half rate. One data sample every two PLL output clock cycles
    // (6)     Normal polarity
    // (7-9)   Termination programmed to be 001
    // (10-11) Comma Alignment enabled
    // (12-14) Loss of signal detection disabled
    // (15-17) First order. Phase offset tracking up to +-488 ppm
    // (18-20) Fully adaptive equalization
    // (22)    Offset compensation enabled
    // (23-24) Loopback disabled
    // (25-27) Test pattern mode disabled
    // (28-31) Reserved

    rxConfig = 0x00440495;
   // rxConfig=0x004404b5;

	// (0)     Enable Transmitter
	// (1-3)   Bus Width 010b (20 bit)
    // (4-5)   Half rate. One data sample every two PLL output clock cycles
	// (6)     Normal polarity
	// (7-10)  Swing max.
	// (11-13) Precursor Tap weight 0%
	// (14-18) Adjacent post cursor Tap weight 0%
	// (19)    Transmitter pre and post cursor FIR filter update
	// (20)    Synchronization master
	// (21-22) Loopback disabled
	// (23-25) Test pattern mode disabled
	// (26-31) Reserved
//    txConfig = 0x000807B5;
  //  txConfig = 0x00000035;
    txConfig = 0x0000015;

 	/* Configure the SRIO SERDES Receive Configuration. */
 	CSL_BootCfgSetSRIOSERDESRxConfig (0, rxConfig);
 	CSL_BootCfgSetSRIOSERDESRxConfig (1, rxConfig);
	CSL_BootCfgSetSRIOSERDESRxConfig (2, rxConfig);
	CSL_BootCfgSetSRIOSERDESRxConfig (3, rxConfig);

	/* Configure the SRIO SERDES Transmit Configuration. */
	CSL_BootCfgSetSRIOSERDESTxConfig (0, txConfig);
	CSL_BootCfgSetSRIOSERDESTxConfig (1, txConfig);
	CSL_BootCfgSetSRIOSERDESTxConfig (2, txConfig);
	CSL_BootCfgSetSRIOSERDESTxConfig (3, txConfig);

    /* Set boot complete back to 1; configuration is complete. */
    CSL_SRIO_SetBootComplete (hSrio, 1);


    /* Loop around until the SERDES PLL is locked. */
    while (1)
    {
        uint32_t    status;

        /* Get the SRIO SERDES Status */
        CSL_BootCfgGetSRIOSERDESStatus (&status);
        if (status & 0x1)
            break;
    }

    /* Clear the LSU pending interrupts. */
    CSL_SRIO_ClearLSUPendingInterrupt (hSrio, 0xFFFFFFFF, 0xFFFFFFFF);

    /* Set the Device Information */
    CSL_SRIO_SetDeviceInfo (hSrio, srio_primary_ID, DEVICE_VENDOR_ID, DEVICE_REVISION);

    /* Set the Assembly Information */
    CSL_SRIO_SetAssemblyInfo (hSrio, DEVICE_ASSEMBLY_ID, DEVICE_ASSEMBLY_VENDOR_ID,
                             DEVICE_ASSEMBLY_REVISION, DEVICE_ASSEMBLY_INFO);

	/* Configure the processing element features*/
	peFeatures.isBridge                          = 0;
	peFeatures.isEndpoint                        = 0;
	peFeatures.isProcessor                       = 1;
	peFeatures.isSwitch                          = 0;
	peFeatures.isMultiport                       = 0;
	peFeatures.isFlowArbiterationSupported       = 0;
	peFeatures.isMulticastSupported              = 0;
	peFeatures.isExtendedRouteConfigSupported    = 0;
	peFeatures.isStandardRouteConfigSupported    = 1;
	peFeatures.isFlowControlSupported            = 1;
	peFeatures.isCRFSupported                    = 0;
	peFeatures.isCTLSSupported                   = 1;
	peFeatures.isExtendedFeaturePtrValid         = 1;
	peFeatures.numAddressBitSupported            = 1;
	CSL_SRIO_SetProcessingElementFeatures (hSrio, &peFeatures);

	/* Configure the source operation CAR */
	memset ((void *) &opCar, 0, sizeof (opCar));
	opCar.portWriteOperationSupport = 1;
	opCar.atomicClearSupport        = 1;
	opCar.atomicSetSupport          = 1;
	opCar.atomicDecSupport          = 1;
	opCar.atomicIncSupport          = 1;
	opCar.atomicTestSwapSupport     = 1;
	opCar.doorbellSupport           = 1;
	opCar.dataMessageSupport        = 1;
	opCar.writeResponseSupport      = 1;
	opCar.streamWriteSupport        = 1;
	opCar.writeSupport              = 1;
	opCar.readSupport               = 1;
	opCar.dataStreamingSupport      = 1;
	CSL_SRIO_SetSourceOperationCAR (hSrio, &opCar);

	/* Configure the destination operation CAR */
	memset ((void *) &opCar, 0, sizeof (opCar));
	opCar.portWriteOperationSupport  = 1;
	opCar.doorbellSupport            = 1;
	opCar.dataMessageSupport         = 1;
	opCar.writeResponseSupport       = 1;
	opCar.streamWriteSupport         = 1;
	opCar.writeSupport               = 1;
	opCar.readSupport                = 1;
	CSL_SRIO_SetDestOperationCAR (hSrio, &opCar);

	/* Set the 16 bit and 8 bit identifier for the SRIO Device. */
	CSL_SRIO_SetDeviceIDCSR (hSrio, DEVICE_ID1_8BIT, DEVICE_ID1_16BIT);

    /* Enable TLM Base Routing Information for Maintainance Requests & ensure that
     * the BRR's can be used by all the ports. */
    CSL_SRIO_SetTLMPortBaseRoutingInfo (hSrio, 0, 1, 1, 1, 0);
	CSL_SRIO_SetTLMPortBaseRoutingInfo (hSrio, 0, 2, 1, 1, 0);

    /* Configure the Base Routing Register to ensure that all packets matching the
     * Device Identifier & the Secondary Device Id are admitted. */
    CSL_SRIO_SetTLMPortBaseRoutingPatternMatch (hSrio, 0, 1, srio_primary_ID, srioIDMask);
    CSL_SRIO_SetTLMPortBaseRoutingPatternMatch (hSrio, 0, 2, srio_secondary_ID, srioIDMask);

    /* We need to open the Garbage collection queues in the QMSS. This is done to ensure that
     * these queues are not opened by another system entity. */
    for (i = 0; i < 6; i++)
    {
        /* Open the Garabage queues */
        queueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, gargbageQueue[i], &isAllocated);
        if (queueHnd < 0)
            return -1;

        /* Make sure the queue has not been opened already; we dont the queues to be shared by some other
         * entity in the system. */
        if (isAllocated > 1)
            return -1;
    }

    /* Set the Transmit Garbage Collection Information. */
    CSL_SRIO_SetTxGarbageCollectionInfo (hSrio, GARBAGE_LEN_QUEUE, GARBAGE_TOUT_QUEUE,
                                         GARBAGE_RETRY_QUEUE, GARBAGE_TRANS_ERR_QUEUE,
                                         GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE);

    /* Set the Host Device Identifier. */
    CSL_SRIO_SetHostDeviceID (hSrio, srio_primary_ID);

    /* Configure the component tag CSR */
    CSL_SRIO_SetCompTagCSR (hSrio, 0x00000000);

	/* Configure the PLM for all the ports. */
	for (i = 0; i < 4; i++)
	{
		/* Set the PLM Port Silence Timer. */
		CSL_SRIO_SetPLMPortSilenceTimer (hSrio, i, 0x2);

		/* TODO: We need to ensure that the Port 0 is configured to support both
		 * the 2x and 4x modes. The Port Width field is read only. So here we simply
		 * ensure that the Input and Output ports are enabled. */
		CSL_SRIO_EnableInputPort (hSrio, i);
		CSL_SRIO_EnableOutputPort (hSrio, i);

		/* Set the PLM Port Discovery Timer. */
		CSL_SRIO_SetPLMPortDiscoveryTimer (hSrio, i, 0x2);

		/* Reset the Port Write Reception capture. */
		CSL_SRIO_SetPortWriteReceptionCapture (hSrio, i, 0x0);

		/* CSR: Set VMIN to 15 as recommended by this post:

		* http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/196080.aspx */

		CSL_SRIO_GetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);
		vminExponentConfig.vminExp = 15;
		CSL_SRIO_SetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);
	}

	/* Set the Port link timeout CSR */
	// CSL_SRIO_SetPortLinkTimeoutCSR (hSrio, 0x000FFF);
	CSL_SRIO_SetPortLinkTimeoutCSR (hSrio, 0xFF0FFF);
	CSL_SRIO_SetPortResponseTimeoutCSR (hSrio, 0xFF0FFF);

	/* Set the Port General CSR: Only executing as Master Enable */
	CSL_SRIO_SetPortGeneralCSR (hSrio, 0, 1, 0);

	/* Clear the sticky register bits. */
	CSL_SRIO_SetLLMResetControl (hSrio, 1);

	/* Set the device id to be 0 for the Maintenance Port-Write operation
	 * to report errors to a system host. */
	CSL_SRIO_SetPortWriteDeviceId (hSrio, 0x0, 0x0, 0x0);

    /* Set the Data Streaming MTU */
    CSL_SRIO_SetDataStreamingMTU (hSrio, 64);

    //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	/* Configure the path mode for the ports. */
    CSL_SRIO_GetBootComplete (hSrio, &bootCompleteFlag);

    if (bootCompleteFlag == 1)
   	/* Set boot complete to be 0; to enable writing to the SRIO registers. */
    CSL_SRIO_SetBootComplete (hSrio, 0);

    /* Configure the path mode for all ports. */
    for (port = 0; port < 4; port++)
   {
    	/* Configure the path mode for the port. */
    	CSL_SRIO_SetPLMPortPathControlMode (hSrio, port, 0x4);// 4x

   }
   if (bootCompleteFlag == 1)
   /* Set boot complete back to 1; configuration is complete. */
   CSL_SRIO_SetBootComplete (hSrio, 1);


	/* Set the LLM Port IP Prescalar. */
	CSL_SRIO_SetLLMPortIPPrescalar (hSrio, 0x1F);

	/* Configure the ingress watermarks */
	for (i = 0; i < 4; i++)
	{
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 0, 0x24, 0x24);
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 1, 0x1B, 0x1B);
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 2, 0x12, 0x12);
		CSL_SRIO_SetPBMPortIngressPriorityWatermark (hSrio, i, 3, 0x9, 0x9);
	}

    /* Disable interrupt pacing for all interrupt destinations. */
    for (i = 0; i < 24; i++)
        CSL_SRIO_DisableInterruptPacing (hSrio, i);


	/* Set all the queues 0 to operate at the same priority level and to send packets onto Port 0 */
    for (i =0 ; i < 16; i++)
    	CSL_SRIO_SetTxQueueSchedInfo (hSrio, i, 0, 0);

#ifdef DRV_DEBUG
    //CSL_SRIO_SetTxQueueSchedInfo (hSrio, 8, 2, 0);
    System_printf ("In TXQueueSched DRV_DEBUG area\n");
    /* All TxQueue scheduled to port 2 (and open all TxQueues, except TxQueue 0, to test assignment)
    for (i =0 ; i < 16; i++)
    {
    	CSL_SRIO_SetTxQueueSchedInfo (hSrio, i, 2, 0);
    	//openQueueValues[i] = Qmss_queueOpen (Qmss_QueueType_SRIO_QUEUE , 672 + i,  &isAllocated); //txQueueNum, &isAllocated);
    	//System_printf ("Opening SRIO queue: %i", openQueueValues[i]);
    }
    */
    /* 1st half of TxQueues (except TxQueue 0) open to test assignment
    for (i =1 ; i < 8; i++) //16; i++)
    {
    	openQueueValues[i] = Qmss_queueOpen (Qmss_QueueType_SRIO_QUEUE , 672 + i,  &isAllocated); //txQueueNum, &isAllocated);
    	System_printf ("Opening SRIO queue: %i\n", openQueueValues[i]);
    }
    */
    openQueueValues[0] = Qmss_queueOpen (Qmss_QueueType_SRIO_QUEUE , 673,  &isAllocated);
    System_printf ("Opening SRIO queue: %i\n", openQueueValues[0]);
	/* Enable the SRIO Transmit channel for each driver instance. */
	{
    	Cppi_CpDmaInitCfg   srioCPDMACfg;
    	Cppi_Handle			cppiHnd;
		Cppi_TxChInitCfg    txCfg;
		Cppi_ChHnd			txChHnd;

	    /* Initialize the SRIO CPDMA config structure. */
	    memset ((void *)&srioCPDMACfg, 0, sizeof(Cppi_CpDmaInitCfg));

	    /* Setup the SRIO CPDMA Configuration and open the SRIO CPDMA instance; this needs to be done
	     * for each instance also; since this can be done on each core.  */
	    srioCPDMACfg.dmaNum = Cppi_CpDma_SRIO_CPDMA;
	    cppiHnd = Cppi_open (&srioCPDMACfg);
	    if (cppiHnd == NULL)
	    {
	    	System_printf ("\n\n\nError: Initializing CPPI for SRIO CPDMA\n\n\n");
	    	//Srio_osalLog ("Error: Initializing CPPI for SRIO CPDMA\n");
	        return NULL;
	    }

	    /* Disable the SRIO-CPDMA Loopback mode in the CPPI */
	    if (Cppi_setCpdmaLoopback (cppiHnd, 0) != CPPI_SOK)
	    {
	    	System_printf ("\n\n\nError: SRIO CPDMA Loopback mode failed\n\n\n");
	        //Srio_osalLog ("Error: SRIO CPDMA Loopback mode failed\n");
	        return -1;
	    }

		/* Open the SRIO Transmit Channel and keep it disabled. */

		//CSR: Testing TxQueue-TxCh alignment
		System_printf ("\n\n\n Setting tx channelNums.\n\n\n");
		txCfg.channelNum   = 1; 			//txCfg.channelNum   = CPPI_PARAM_NOT_SPECIFIED;

		txCfg.priority = Srio_PktDma_Prio_Low; //based on DmaTxPrio set in benchmarking.c being set to lowest

		txCfg.txEnable     = Cppi_ChState_CHANNEL_DISABLE;
		txCfg.filterEPIB   = 0;
		txCfg.filterPS     = 0;
		txCfg.aifMonoMode  = 0;
		txChHnd = Cppi_txChannelOpen (cppiHnd, &txCfg, &isAllocated);
		if (txChHnd == NULL)
		{
			System_printf ("\n\nError: Opening SRIO Tx channel %d failed\n\n", txCfg.channelNum);
			//Srio_osalLog ("Error: Opening SRIO Tx channel %d failed\n", txCfg.channelNum);
			return NULL;
		}
	    /* Configure the Transmit Queue Threshold. */
	    Qmss_setQueueThreshold (673, 1, 1);

	    /* Enable the Transmit Channel. */
	    if (Cppi_channelEnable (txChHnd) < 0)
	    {
	    	System_printf ("\n\n\nError: Enabling SRIO Tx Channel failed\n\n\n");
	        //Srio_osalLog ("Error: Enabling SRIO Tx Channel failed\n");
	        return NULL;
	    }
	}

#endif

#if 0
    /* Set the Doorbell route to determine which routing table is to be used 
     * This configuration implies that the Interrupt Routing Table is configured as 
     * follows:-
     *  Interrupt Destination 0 - INTDST 16 
     *  Interrupt Destination 1 - INTDST 17 
     *  Interrupt Destination 2 - INTDST 18
     *  Interrupt Destination 3 - INTDST 19 */
    CSL_SRIO_SetDoorbellRoute (hSrio, 0);
#else
    /* Set the Doorbell route to determine which routing table is to be used
     * This configuration implies that the Interrupt Routing Table is configured as
     * follows:-
     *  Interrupt Destination 0 - INTDST 0
     *  Interrupt Destination 1 - INTDST 1
     *  Interrupt Destination 2 - INTDST 2
     *  Interrupt Destination 3 - INTDST 3 */
   	CSL_SRIO_SetDoorbellRoute (hSrio, 1);
#endif

    /* Route the Doorbell interrupts. 
     *  Doorbell Register 0 - All 16 Doorbits are routed to Interrupt Destination 0. 
     *  Doorbell Register 1 - All 16 Doorbits are routed to Interrupt Destination 1. 
     *  Doorbell Register 2 - All 16 Doorbits are routed to Interrupt Destination 2. 
     *  Doorbell Register 3 - All 16 Doorbits are routed to Interrupt Destination 3. */
    for (i = 0; i < 16; i++)
    {
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 0, i, 0);
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 1, i, 1);
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 2, i, 2);
        CSL_SRIO_RouteDoorbellInterrupts (hSrio, 3, i, 3);
    }

	/* Enable the peripheral. */
	CSL_SRIO_EnablePeripheral (hSrio);

    /* Configuration has been completed. */
    CSL_SRIO_SetBootComplete (hSrio, 1);


    /* Check Ports and make sure they are operational. */
    //////!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

    /* Wait for all SRIO ports for specified lane mode to be operational */
    printf ("Debug: Waiting for SRIO ports to be operational...  \n");
    tscTemp = CSL_tscRead () + 5000000000;
    for (port = 0; port < 4; port++)
    {
     	if ((0x1 >> port) & 0x1 == 1)
       	{
       		sprintf (statusText, "NOT ");
       		/* Check for good port status on each valid port, timeout if not received after 5 seconds */
       	    while (CSL_tscRead() < tscTemp)
       	    {
    			if (CSL_SRIO_IsPortOk (hSrio, port) == TRUE)
    			{
    				sprintf (statusText,"");
    				break;
    			}
       	    }
        	    printf ("Debug: SRIO port %d is % soperational.\n", port, statusText);
        		tscTemp = CSL_tscRead() + 1000000000;
        }
   }

    /* Initialization has been completed. */
    return 0;
}