If an I2C_transfer specifies a write followed by a read, will there be two completely separate I2C bus transactions or will a repeated start be used?
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If an I2C_transfer specifies a write followed by a read, will there be two completely separate I2C bus transactions or will a repeated start be used?
It should be a repeated start, though it shouldn't matter to your I2C peripheral. From an RTOS task perspective it is atomic.
Thanks for your help.
I think that most peripherals are going to be tolerant of a stop then start in place of a repeated start, but I believe that in some instances the governing spec really does indicate repeated start. For example, isn't that what PMBus uses for things like ReadByte?
In our situation (single master bus), it really isn't too important, but if you have a PMBus peripheral on a multi-master bus, it can be necessary in order to assure that another master doesn't interfere with your command.
It would be nice to know for sure that I2C_transfer will use a repeated start.
Jim,
I believe the TI-RTOS documentation states that the I2C driver does not support a multi-master bus. I've submitted an enhancement request (SDOCM00113569) to add this support.
I haven't used PMBus specs yet, so I don't know to what extent the I2C driver is compatible with the PMBus specs.
What device are working with? On TivaC, CC3200, and MSP430 [E]USCI devices, I am certain that for those devices the I2C driver issues an actual repeated start bit.
I'm using a Tiva device - TM4C1231DSPZ. It sounds like I'll get a repeated start, then. That sounds great.
Thank you!