Missing timing parameters in DM3730 documentation

Hi,

Do you have a document containing timing parameters for SDRC controller inside DM3730? Datasheet contains only PCB guidelines.

I am asking because our team prepared DM3730 based module with MT46H64M32LFCM-6 IT SDRAM memory. And we have problems - bit errors occur when data is transferred from SD card. Soldering new SDRAM chip reduces / vanishes the phenomena, so we believe there may be timing incompatibility. Our PCB meets criteria described in DM3730 datasheet.

By the way, are there any known interoperability issues with certain DDR memories?

Pawel

PS: L3 clock is set acccordingly to get DDR333 rate (166MHz). Verified using oscilloscope.