DM3725 Power-up sequence

Sergey Chub

Hello.

I need to know the exact timing of the power-up sequence (or at least the ballpark) but I can't find these numbers anywhere in the technical documentation. The reason I need to know this is, I'm planning to connect a parallel NOR-flash device to the processor, and the flash IC I've chosen requires at least 30us of asserted reset after its VCC has ramped up. Considering how the two devices work tightly in pair, it is only logical that I should use the processor reset for this purpose. The question is, can I? And if I can, which one? Power-On Reset or Warm Reset?

Thank you

over 10 years ago

0 Cvetolin Shulev-XID over 10 years ago

TI__Guru 65405 points

Hi Sergey,

If you are using the power-up sequence as shown in the TRM Figure 3-28 the timings can be determined by the sys_32k and OSC_CLK clocks which are available after the first stage of the sequence. The timings during the first stage are asserted by the external power IC and therefore this diagram does not give information about timings.

Tsvetolin Shulev

0 Sergey Chub over 10 years ago in reply to Cvetolin Shulev-XID

Intellectual 400 points

Yeah, of course I should have looked in the PMIC's documentation. I don't know how I missed that... I'm just a moron. Very sorry about that.

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DM3725 Power-up sequence