Hello!
I tried to tramsfer 16 subframes from DDR to L2 one by one using QDMA on 6748, but it doesn't work in my application.
The size of frame is 1600*480, and the size of subframe is 100*480.I check the QEESR,it always be 0,and i can't write 1 to it. As result ,the QDMA does'nt work. How can solve this problem, please help me and tell more detailedly!
Best regard!
The following is my CODE for one subframe:
unsigned int Qdma3toL2()
{
unsigned int chType_l2= EDMA3_CHANNEL_TYPE_QDMA;
unsigned int chNum_l2= 2;
unsigned int tccNum_l2= 2;
unsigned int edmaTC_l2= 2;
unsigned int syncType_l2= EDMA3_SYNC_A;
unsigned int paRAMId_l2 = 2u;//一共128个
unsigned int trigMode_l2 = EDMA3_TRIG_MODE_QDMA;
unsigned int evtQ_l2 = 0; // 使用的事件队列
unsigned int opt_l2 = 0;
volatile unsigned int index = 0u;
volatile unsigned int count = 0u;
EDMA3CCPaRAMEntry paramSet;
unsigned int retVal = 0u;
unsigned int numenabled = 0u;
unsigned int acnt = 100;
unsigned int bcnt = 480;
unsigned int ccnt = 1;
unsigned int dstBuffAddr = 0;
srcBuff = (char *)(image+1);//_srcBuff;
dstBuff = (char *)(pbufA);//_dstBuff;
/* Request DMA channel and TCC */
retVal = EDMA3RequestChannel(SOC_EDMA30CC_0_REGS, chType_l2, chNum_l2, tccNum_l2, evtQ_l2);
EDMA3MapQdmaChToPaRAM(SOC_EDMA30CC_0_REGS, chNum_l2, &paRAMId_l2);
EDMA3SetQdmaTrigWord(SOC_EDMA30CC_0_REGS, chNum_l2, EDMA3CC_PARAM_ENTRY_DST);
/* ************* REGISTER THE CALL BACK FUNCTION HERE ******************* */
cb_Fxn[tccNum_l2] = &callback; /* Registering Callback Function */
irqRaised = 0u;
if (TRUE == retVal)
{
/* Fill the PaRAM Set with transfer specific information */
paramSet.srcAddr = (unsigned int)(srcBuff);
paramSet.destAddr = (unsigned int)(dstBuff);
paramSet.aCnt = 100;
paramSet.bCnt = 480;
paramSet.cCnt = 1;
paramSet.srcBIdx = 1600;
paramSet.destBIdx = 100;
paramSet.srcCIdx = 0;
paramSet.destCIdx = 0;
paramSet.linkAddr = (unsigned short)0xFFFFu;
paramSet.bCntReload = (unsigned short)0u;
/*CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
0, CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_EN, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR );*/
paramSet.opt = 0x00100008;
opt_l2= paramSet.opt;
EDMA3QdmaSetPaRAM(SOC_EDMA30CC_0_REGS, chNum_l2, paRAMId_l2, ¶mSet);
}
retVal = FALSE;
retVal = EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, chNum_l2, EDMA3_TRIG_MODE_QDMA);
dstBuffAddr = (unsigned int)EDMA3QdmaGetPaRAMEntry(
SOC_EDMA30CC_0_REGS, paRAMId_l2, EDMA3CC_PARAM_ENTRY_DST);
EDMA3QdmaSetPaRAMEntry(SOC_EDMA30CC_0_REGS, paRAMId_l2,
EDMA3CC_PARAM_ENTRY_DST, dstBuffAddr);
/* Wait for the Completion ISR. */
while (irqRaised == 0u)
{
}
/* Check the status of the completed transfer */
if (irqRaised < 0)
{
/* Some error occured, break from the FOR loop. */
UARTPuts("\r\nQdma3Test: Event Miss Occured!!!\r\n", -1);
/* Clear the error bits first */
EDMA3ClearErrorBits(SOC_EDMA30CC_0_REGS, chNum, evtQ);
// break;
}
return TRUE;
}
