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Problem about clear dm8168 mcbsp SPCR1 RSYNC_ERR

Xavier
Genius 3180 points
Other Parts Discussed in Thread: SYSCONFIG

Hi all:

    We use dm8168 soc, and mcbsp is used,

    In our mcbsp receive irq, we found the RSYNC_ERR bit clear failure,

    the follow is our code

    irqst_spcr1 = MCBSP_ARG_READ(OMAP_MCBSP_REG_SPCR1);
    if (irqst_spcr1 & RSYNC_ERR)
    {

      MCBSP_ARG_WRITE(OMAP_MCBSP_REG_SPCR1,irqst_spcr1&(~RSYNC_ERR));

    }

   why this bit can not be cleaned by set bit 0 as TRM telled,

   And only set       OMAP_MCBSP_REG_SYSCON as follow,

     MCBSP_ARG_WRITE(OMAP_MCBSP_REG_SYSCON, 2);

best regards

xavier

  • 0
    TI__Guru**** 170625 points

    Hi Xavier,

    Xavier said:
    We use dm8168 soc

    Are you using DM8168 EVM or DM8168 custom board?

    Xavier said:
    OMAP_MCBSP_REG_SPCR1

    Is this the SPCR1_REG at 0x47000114 address?

    Xavier said:
    RSYNC_ERR

    Is the value behind RSYNC_ERR 0x8 (0b1000) or other?

    Xavier said:
    OMAP_MCBSP_REG_SYSCON

    I can not find such register in the DM816x TRM McBSP register map. Is this the SYSCONFIG_REG at 0x47000010 address?

    Xavier said:
    MCBSP_ARG_WRITE(OMAP_MCBSP_REG_SPCR1,irqst_spcr1&(~RSYNC_ERR))

    Xavier said:
    why this bit can not be cleaned by set bit 0 as TRM telled

    Can you try to clear it with writing 1 to it?

    Can you also see if IRQSTATUS[0] RSYNCERR (at addr 0x47000028) bit is set when you have this SPCR1_REG[3] RSYNCERR bit set?

    Can you also see if IRQSTATATUS[0] RSYNCERR (at addr 0x470001A0) bit is set when you have this SPCR1_REG[3] RSYNCERR bit set?

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Genius 3180 points

    we design our own dm816 board,

    SPCR1 reg address is 47000014, we found some version of TRM made a mistake as the address all add 0x100,

    so you may found that the address is 47000114.

    RSYNCERR is 0x08, i do set 470000A0 RSYNC_ERR bit, no effect,

    i do not try 47000028

  • 0 in reply to Xavier
    TI__Guru**** 170625 points

    Xavier,

    You are right for the addresses, the DM816x TRM is not fully correct:

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/243306/852991.aspx#852991

    Thus we have:

    0x47000014 SPCR1_REG[3] RSYNCERR - for legacy mode

    0x470000A0 IRQSTATUS[0] RSYNCERR

    When you enter the ISR, you have SPCR1_REG[3] RSYNCERR bit set to 1, but what about IRQSTATUS[0] RSYNCERR bit? Is it also set to 1?

    SPCR1_REG[3] RSYNCERR bit can be cleared when write 0 OR by a receiver reset. So can you try do receiver reset to clear that bit?

    Can you also provide the flow to set SPCR1_REG[3] RSYNCERR bit to 0x1?

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Genius 3180 points

    I cleared SPCR1_REG[3] RSYNCERR by  write 0,

    it does not works at all,

    i also clear SPCR1_REG[0] to do reset in irq fun, it does not works too,

    finally i set REG_SYSCON 2 to rest the whole mcbsp and reInit it works,

    but i do not why clear SPCR1_REG[3] RSYNCERR has no effect at all

    best regards

    xavier