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C6678 PCIe Address Translation

I am using the PCIe example code under "C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\pcie\example\sample" and  "pcie_sample.c" to understand how to interface C6678 (RC)  to our SPARTAN6 FPGA (EP)  using the PCIe. In the example, they are using C6678 EVM and address translation is enabled. in my case, we instantiated a 4K DPRAM and want to read the contents into the C6678 Multicore shared memory or DDR3 so all cores can access the same data. Any advice on how to change the code to achieve this specially the address translation part?

Regards,

Murad

  • Hi Murad,

    Please take a look at "pcie_sample.h" file and modified the Master side(RC) Inbound/Outbount address. 

    Inbound address translation is used to remap accepted incoming accesses from other PCIe devices to locations within the device's memory map.

    Outbound Address Translation maps internal bus address to PCIe address space. This is accomplished by using outbound address translation logic. For each outbound read/write request, the address translation module within the PCIESS can convert an internal bus address to a PCIe address of memory read/write type. For more information refer PCIe Users Guide.

    In the MCSDK PCIe sample example, two DSP EVMs are used to test the PCIe driver. DSP 1 is configured as a Root Complex and DSP 2 is configured as End Point.

    Once the PCIe link is established, the following sequence of actions will happen:

    1. DSP 1 sends data to DSP 2 - DSP 2 waits to receive all the data

    2. DSP 2 sends the data back to DSP 1

    3. DSP 1 waits to receive all the data

    4. DSP 1 verifies if the received data matches the sent data and declares test pass or fail.

    Thanks,

  • Thanks Ganapathi,

    To be honest, I've been reading about PCIe and address translation and looking at the code you mentioned and "PCIe Use Cases for KeyStone Devices_sprabk8" over and over...the more I read, the more I get confused :-(...So, since the FPGA DPRAM has address range from 0 to 4095, do I need to just change the:

    #define PCIE_OB_LO_ADDR_M 0x70000000

    to

    #define PCIE_OB_LO_ADDR_M 0x00000000

    ???

     

    Do you have a good example that shows how to interface C6678 to SPARTAN6 using PCIe

     

    Regards,

     

    Murad

     

  • Hi Murad,

    Yes, your changes are correct.

    TI not provide the exact example. Please refer MCSDK pcie_example project and develope your test code.

    Thanks,

  • Thanks alot Ganapathi for your prompt reply

    Regards, 

    Murad