About using AUXOSC as the video reference clock

Sivan,

Sivan Tse said:

we use AUXOSC (27MHz external crystal) as the reference clock

 On the DM814x EVM we have DEVOSC at 20MHz and AUXOSC at 22.579MHz. The Device (DEVOSC) clock is used to generate the majority of the internal reference clocks, while the Auxiliary (AUXOSC) clock can optionally be used as a source for the Audio and/or Video PLLs. AUXOSC is needed when a specific frequency is required for the design, for example video 27MHz, audio 22.579MHz, etc.

Sivan Tse said:

The following is our modified code:

/var/works/DVRRDK_04.00.00.03/ti_tools/linux_lsp/kernel/linux-dvr-rdk/drivers/video/ti81xx/vpss/system.c:

#define TI814X_OSC_FREQ (27 * MHZ) //20

DVRRDK_04.00.00.03/ti_tools/hdvpss/dvr_rdk_hdvpss/packages/ti/psp/platforms/ti8107/src/vps_platformTI8107.c
#define VPS_TI8107_EVM_OSC_FREQ (27u * VPS_TI8107_MHz) //20u

I think the above code change is not correct (DEVOSC from 20MHz to 27MHz), as in your board (if my understanding is correct) you keep the DEVOSC at 20MHz and change the AUXOSC from 22.579MHz to 27MHz. Thus you need to change only the reference to AUXOSC 22.579MHz to 27MHz, as you did in the below code:

Sivan Tse said:

DVRRDK_04.00.00.03/ti_tools/linux_lsp/kernel/linux-dvr-rdk/arch/arm/mach-omap2/clock814x_data.c:

/* Additional clock source */
static struct clk osc1_clkin_ck = {
.name = "osc1_clkin_ck",
.ops = &clkops_null,
.rate = 27000000, //22579000, /* Typically at 27M or 22.579MHz */
.flags = RATE_IN_TI814X | RATE_IN_DM385 | RATE_IN_TI811X,
};

Regards,
Pavel

Hi Pavel,

Thanks for your reply.

Yes, you are right. In our board, we keep the DEVOSC at 20MHz and change the AUXOSC to 27MHz.

But I think TI814X_OSC_FREQ and VPS_TI8107_EVM_OSC_FREQ should be 27MHz, because they were used to calculate the PLL divider values(Please refer to the code of system_getdividers() and vps_getDividers()), set 20MHz will get  wrong divider values.

Sivan,

The current configuration in the linux kernel is:

DEVOSC -> DPLL_VIDEO0 -> HDVPSS SD_VENC (sd_venc_ck = 250MHz)

DEVOSC -> DPLL_VIDEO1 -> HDVPSS VOUT0 (hd_venc_g_ck = 20MHz)

DEVOSC -> DPLL_VIDEO2/HDMI -> HDMI (hdmi_dpll_ck = 270MHz)

DEVOSC -> DPLL_DSS/HDVPSS -> HDVPSS/DSS (hdvpss_proc_fck = 200MHz, hdvpss_proc_d2_fck = 100MHz).

Please let me know which DPLL exactly you need to change the source from DEVOSC to AUXOSC? DPLL_VIDEO0, DPLL_VIDEO1, DPLL_VIDEO2/HDMI or DPLL_DSS/HDVPSS?

And what frequency you need on the output of this DPLL?

For more details see DM814x TRM, sections 2.3.3 Main PLL Clock Structure (for DPLL_DSS/HDVPSS) and 2.3.7 Video PLL Clock Structure for DPLL_VIDEO0/1/2

Regards,
Pavel

Sivan,

Sivan Tse said:

DVRRDK_04.00.00.03/ti_tools/linux_lsp/kernel/linux-dvr-rdk/arch/arm/mach-omap2/board-ti8148evm.c:

static void __init ti8148_evm_init(void)

{

...

//change clk parent

struct clk *parent, *child;

parent = clk_get(NULL, "osc1_clkin_ck");
child = clk_get(NULL, "video1_dpll_clkin_ck");
clk_set_parent(child, parent);
clk_put(child);
clk_put(parent);

}

When I do this from my side, I have:

AUXOSC (22.579MHz) -> DPLL_VIDEO1

osc1_clkin_ck -> video1_dpll_clkin_ck -> video1_dpll_ck -> hd_venc_g_ck

And the frequency of the DPLL_VIDEO1 output is the same as the frequency in the input, it is 22579000 Hz.

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

What frequency you need on the DPLL_VIDEO1 output, is it 27MHz or other value?

Regards,
Pavel

Pavel Botev said:

Sivan,

DVRRDK_04.00.00.03/ti_tools/linux_lsp/kernel/linux-dvr-rdk/arch/arm/mach-omap2/board-ti8148evm.c:

static void __init ti8148_evm_init(void)

{

...

//change clk parent

struct clk *parent, *child;

parent = clk_get(NULL, "osc1_clkin_ck");
child = clk_get(NULL, "video1_dpll_clkin_ck");
clk_set_parent(child, parent);
clk_put(child);
clk_put(parent);

}

When I do this from my side, I have:

AUXOSC (22.579MHz) -> DPLL_VIDEO1

osc1_clkin_ck -> video1_dpll_clkin_ck -> video1_dpll_ck -> hd_venc_g_ck

And the frequency of the DPLL_VIDEO1 output is the same as the frequency in the input, it is 22579000 Hz.

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide

What frequency you need on the DPLL_VIDEO1 output, is it 27MHz or other value?

Regards,
Pavel

[/quote]

Hi Pavel,

Here is the configuration we wanted: AUXOSC (27MHz) -> DPLL_VIDEO1 -> HDVPSS VOUT0

When use DEVOSC as the DPLL_VIDEO1 clock source, we could not obtain an accurate pixel clock frequency for same special resolutions such as 1080I59.94(74.176MHz)、1080P59.94(148.352MHz). We want to use AUXOSC to produce a precise video pixel clock for VOUT0.

I think I've found the cause of the problem: when i changed TI814X_OSC_FREQ to 27MHz, the function system_getdividers() return -EINVAL, it led to the PLL setting failed in function Vps_system_setpll().

Could you tell me how to fix it?

Best Regards,

Sivan

Sivan,

Sivan Tse said:

When use DEVOSC as the DPLL_VIDEO1 clock source, we could not obtain an accurate pixel clock frequency for same special resolutions such as 1080I59.94(74.176MHz)、1080P59.94(148.352MHz). We want to use AUXOSC to produce a precise video pixel clock for VOUT0.

This is correct.

Sivan Tse said:

Here is the configuration we wanted: AUXOSC (27MHz) -> DPLL_VIDEO1 -> HDVPSS VOUT0

Sivan Tse said:

I think I've found the cause of the problem: when i changed TI814X_OSC_FREQ to 27MHz, the function system_getdividers() return -EINVAL, it led to the PLL setting failed in function Vps_system_setpll().

I do not think that function system_getdividers() from /drivers/video/ti81xx/vpss/system.c file is configuring anything related to DPLL_VIDEO1. This function/file is related to some of the other video PLLs (DPLL_VIDEO0, DPLL_VIDEO2/HDMI, DPLL_DSS/HDVPSS), but not to the DPLL_VIDEO1. I state this by the fact that DPLL_VIDEO1 is not locked, but is in bypass mode, thus provides the input frequency (20MHz, 22.579MHz or 27MHz) to the output without change/increase it.

See also the below e2e thread for info regarding DPLL_VIDEO1:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/335756.aspx

Regards,
Pavel

Sivan,

Have you tried to set the desired frequency (74.176MHz, 148.352MHz) though the clock framework?

http://processors.wiki.ti.com/index.php/TI81XX_PSP_PM_CLOCK_FRAMEWORK_User_Guide#Change_clock_rate_2

Regards,
Pavel

Pavel,

Pavel Botev said:

Have you tried to set the desired frequency (74.176MHz, 148.352MHz) though the clock framework?

I went through this same exercise about a month ago.  I used the clock framework to change the parent of "hdmi_dpll_clkin_ck" to "osc1_clkin_ck" in the board-ti8148.c file.  But, as Sivan indicated, I found system.c hard-coded to use 20 MHz - and directly accessing clock registers, totally bypassing the clock framework.  So, among its many limitiations, is no FRACTIONAL_M seting, so it's more difficult to match DTV and VESA clock settings starting from 27 MHz.

Why does system.c not use the clock framework?  If it did, then Sivan's change would be much easier.  Is the clock framework broken in some way with regards to the video clocking?

Dan -

Dan,

I can provide you the below pointers, may be these will be in help:

https://gitorious.org/rowboat/kernel/source/74cad6beac8a2454731ab86c54c9225f3c66d726:drivers/video/ti81xx/vpss/system.c

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/273394.aspx

Regards,
Pavel