All TMS320C6678 cores are running, but only core 0 uses the EDMA. EDMA gets used by core 0 only during a PCIe MSI interrupt service routine. This PCIe MSI fires at a rate of 30Hz (every 33.3ms). The interrupt service routine (ISR) does one of the following:
1) Process data, EDMA transfer resulting 2 buffers to PCIe, or
2) EDMA previous result from DDR to PCIe, process data, store resulting 2 buffers to DDR
The EDMA transfer consists of the following operations, using ti/csl/csl_edma3.h:
1) Wait for IPR bit 0 to go high.
2) Set up PaRAM for channel 0. CC1 TC3 is used. There are 2 PaRAM entries. Each entry uses AB synchronization with CCNT > 1. Intermediate transfer complete chaining is enabled. Transfer complete chaining is enabled on the first entry, disabled on the second entry. Intermediate completion interrupt is disabled. Transfer completion interrupt is disabled on first entry, enabled on second entry. TCC is 0 (same as channel). Transfer completion is normal.
3) IPR bit 0 is cleared.
4) Channel 0 is triggered.
5) In ISR case 2, wait for IPR bit 0 to go high.
When ISR is switched via PCIe from case 1 to case 2, the first wait exits, but the second wait never exits, indicating that IPR bit 0 is stuck low. EMR, EMRH, and QEMR shows that there is a missed event for channel 0: EMR bit 0 = 1, all other bits = 0. SER and SERH shows that channel 0 is in the queue: SER bit 0 = 1, all other bits = 0. CCERR shows no TCC errors and no queue threshold errors: CCERR = 0.
It should be noted that the ISRs take roughly 3ms to execute, and it is expected that the DMA takes much less than 30ms to complete. The DMA is used to transfer 1 50 kilobyte buffer from DDR to PCIe, and 1 12.5 kilobyte buffer from DDR to PCIe.
What is causing IPR bit to get stuck low while EMR bit 0 is stuck high?
