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DM8148. Send captured data to DSP, process an send back to HDVPSS for displaying

Marat Shchuchinsky
Expert 2595 points

Hello TI' teams.
Because my question from here:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/374924.aspx

asked ~3 weeks ago and anybody not answer yet, I'll try ask again:
what is the best way for send captured data to DSP,
modify the captured data by DSP algorithm and via output queue of DSP link, return back the
buffer to HDVPSS subsystem for displaying modified data and color conversion (YUV422 to YUV420)?

My dev.platform - DM8148 with dvr-rdk version 3.5 from udworks

  • 0
    TI__Guru* 80190 points

    Hello,

    I notified the DVR RDK team for help.

    Best Regards,

    Margarita

  • 0 in reply to Margarita Gashova
    TI__Mastermind 22946 points

    Please follow the 4D1 VACP+VENC_DEC+DIS use case example. You can go through the file dvr_rdk\mcfw\src_linux\mcfw_api\usecases\ti814x\multich_progressive_4d1_vcap_venc_vdec_vdis.c to underatnd the process flow.

    Regards,

    Manisha

  • 0 in reply to Manisha Agrawal
    Expert 2595 points

    Hello manisha,

    thanX alot for your reply, but thats not exact what I asked. My target use-case more complicated then  on screen display only. I can't return back processed buffer to previous link, my DSP link has output queue (final version - number of output queues) and buffer after processing will be sends to relevant output queue corresponds to processing results.

    Pleaese let me know is this problem send captured video buffer back to HDVPSS via output queue of DSP link? 

  • 0 in reply to Marat Shchuchinsky
    TI__Guru**** 475545 points

    Hi Marat,

     

    This example shows how to transfer a frame from one core to the other core, You could take this as a reference and write a chain for transferring frames to the DSP..

    There is no problem in getting back data from one core to the other core. In this example, captured frames on M3 is tranferred to another core and this frames comes back after processing to the M3 for the display.

     

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Expert 2595 points

    Hi Brijesh,
    thanX alot for your reply.

    Small addendum:

    when my DSP link sends buffers via output queue and connected to encoder via IPC links as is followed:
    ... -> SYSTEM_LINK_ID_OPGAL_ALG_0 -> SYSTEM_DSP_LINK_ID_IPC_FRAMES_OUT_0 -> SYSTEM_VIDEO_LINK_ID_IPC_FRAMES_IN_0 -> SYSTEM_LINK_ID_VENC_0 -> ...
    my usecase works fine.

    But when I make changes in connections and connect DSP link back to HDVPSS as is followed:
    ... -> SYSTEM_LINK_ID_OPGAL_ALG_0 -> SYSTEM_DSP_LINK_ID_IPC_FRAMES_OUT_0 -> SYSTEM_VPSS_LINK_ID_IPC_FRAMES_IN_0 -> SYSTEM_VPSS_LINK_ID_DUP_0 -> SYSTEM_LINK_ID_DEI_HQ_0 ->....
    my usecase hangs (please detail description here: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/374924.aspx)

    Can you please explain me why this problem occured? Why IPC into mcfw isn't symmetry?